xvi Preface
Organization of the Book
The book is organized into three parts: interconnection networks for multi-
processors, packet networks, and data centers. The first part is dedicated to
the basics of communications for multiprocessor systems, and the different
interconnection networks used in this field. The larger portion of the book
discusses interconnection networks for packet switching, and the third part, a
brief introduction to data center interconnection networks. Each of the three
parts of the book can be read separately but consideration of the three parts
may enhance the understanding of how interconnection networks work and
what their design philosophies are, and it may also provide the reader with a
wider scope of applicability of these networks.
These three parts have been put together to offer an overall view on how
interconnection networks operate and their design key points. The book, how-
ever, discusses packet networks in much more depth than the two other top-
ics. The first part of the book introduces the conventional and well-known
interconnection networks for multiprocessor systems and some of the rout-
ing mechanisms used in them (Chapters 1 and 2). These routing mechanisms
exploit the parallelism, symmetry, and modularity of these interconnections.
In the second part of the book, Chapter 3 presents IP lookup as an in-
troduction to packet switching. This chapter discusses the role of memory
in building forwarding tables and schemes to make IP lookup more efficient.
Chapter 4 discusses packet classification, which is a topic very much used in
filtering and identifying packets in almost every network in the Internet.
Chapter 5 covers the basics of packet switching, to introduce the reader
with the terms and metrics used to analyze the performance of packet switches.
Chapter 6 presents input-queued packet switches, which are a very popular
and practical architecture in network equipment manufacturers.
Chapter 7 discusses shared-memory switches, which uses memory as part
of the switching system (or fabric). The chapter discusses several practical
strategies to minimize the use of memory speedup and also some techniques
used to avoid memory hogging by misbehaving users.
Chapter 8 discusses internally buffered packet switches. This switch ar-
chitecture, as in shared-memory switches have memory in the switch fabric,
show many of its advantages over other switch architectures and also show
that it can be used to relax timing constraints for the transmission of high
data rates.
Chapter 9 presents load-balanced packet switches. These packet switches
are among the most recently developed. This chapter reviews these architec-
tures and highlights the remaining challenges to make them a reality.
Chapter 10 presents Clos-network switches. Different from the other switch
architectures, Clos networks are used for building very large switches as the
other architectures cannot scale up.