MT41K256M16HA DDR3L SDRAM: 1.35V Low-Voltage DDR3内存

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MT41K256M16HA是一款低电压DDR3L SDRAM（简称DDR3L）芯片，其工作电压为1.35V，是DDR3标准的1.5V版本的一个变种。该产品在设计上注重兼容性，能够在1.5V电压兼容模式下运行，并支持DDR3L设备在1.5V应用中的向后兼容。以下是MT41K256M16HA的关键特性和功能： 1. 电源电压：该芯片支持双电压供电，即VDD = VDDQ = 1.35V，同时兼容1.5V±0.075V的电压范围，这意味着它可以在多种应用场景中灵活运用。 2. 数据传输：采用差分双向数据 strobe（地址和命令信号），提供了8位预取（8n-bit prefetch）架构，提高数据传输效率。 3. 时序控制：内部包含8个独立的银行，支持可编程的 CAS (Column Address Strobe) 读取延迟（CL，Column Address Strobe Latency），写入延迟（CWL，Write CAS Latency）以及附加写入延迟（AL，Additive Latency）。默认的burst length (BL) 是8，同时可以通过模式寄存器集(MRS)实现突发长度选择，支持BL8或BC4（burst chop）的动态切换。 4. 内存管理：提供自动确定（ODT，Output Driver Test）功能，用于数据、strobe和mask信号的信号强度控制。此外，还支持自我刷新模式（Self-Refresh），在不同温度下有不同的刷新周期，如0°C到+95°C之间的64ms刷新周期和+85°C到+95°C之间的32ms周期。 5. 温度自适应：芯片内置了自刷新温度（SRT，Self-Refresh Temperature）检测机制，以及自动自我刷新（ASR，Automatic Self-Refresh）功能，确保在极端条件下仍能保持正常工作。 6. 优化功能：包括写电平调整（Write Leveling）和多功能寄存器，这些特性有助于优化内存性能，提升稳定性并降低功耗。 MT41K256M16HA是一款专为低电压环境设计的高性能DDR3L SDRAM，通过多种特性确保了兼容性、效率和可靠性，适用于各种需要高效存储解决方案的应用场景，例如计算机系统、嵌入式设备和移动平台等。

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 (Top View)

1234 67895

DDQ

SSQ

REFDQ

ODT

SSQ

DQ2

NF, DQ6

DDQ

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

NF, DQ7

CK#

A10/AP

A15

A12/BC#

A11

A14

DDQ

SSQ

DDQ

CKE

SSQ

DQ3

NF, DQ5

REFCA

BA1

Notes:

1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef85af8fa8

4Gb_DDR3L.pdf - Rev. N 12/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 117).

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

BA[2:0] are referenced to V

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW)

internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/

disabled is dependent upon the DDR3 SDRAM configuration and operating mode.

Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations

(all banks idle), or active power-down (row active in any bank). CKE is synchronous

for power-down entry and exit and for self refresh entry. CKE is asynchronous for

self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are

disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disa-

bled during SELF REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.

Although the DM ball is input-only, the DM loading is designed to match that of the

DQ and DQS balls. DM is referenced to V

REFDQ

. DM has an optional use as TDQS on

the x8.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,

and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is

ignored if disabled via the LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

and

DC LOW ≤ 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef85af8fa8

4Gb_DDR3L.pdf - Rev. N 12/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A[14:13], A12/BC#,

A11, A10/AP, A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 117).

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

BA[2:0] are referenced to V

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-

pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE

LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks

idle),or active power-down (row active in any bank). CKE is synchronous for power-

down entry and exit and for self refresh entry. CKE is asynchronous for self refresh

exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during

POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF

REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS# pro-

vides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to V

REFCA

LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte

input data is masked when LDM is sampled HIGH along with the input data during a

write access. Although the LDM ball is input-only, the LDM loading is

designed to match that of the DQ and DQS balls. LDM is referenced to V

REFDQ

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,

LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,

and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for

the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is

referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

and

DC LOW ≤ 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

4Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef85af8fa8

4Gb_DDR3L.pdf - Rev. N 12/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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