"AD9653-4通道125MSPS高速ADC数据表及规格变更信息" - CSDN文库

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AD9653 Data Sheet

Rev. F | Page 8 of 41

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.

Table 5.

Parameter

1

Temp Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL

Differential Input Voltage

2

Full 0.2 3.6 V p-p

Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V

Input Common-Mode Voltage Full 0.9 V

Input Resistance (Differential) 25°C 15 kΩ

Input Capacitance 25°C 4 pF

LOGIC INPUTS (PDWN, SYNC, SCLK)

Logic 1 Voltage

Full

1.2

AVDD + 0.2

V

Logic 0 Voltage Full 0 0.8 V

Input Resistance 25°C 30 kΩ

Input Capacitance 25°C 2 pF

LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V

Logic 0 Voltage Full 0 0.8 V

Input Resistance 25°C 26 kΩ

Input Capacitance 25°C 2 pF

LOGIC INPUT (SDIO)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V

Logic 0 Voltage

Full

0

0.8

V

Input Resistance 25°C 26 kΩ

Input Capacitance 25°C 5 pF

LOGIC OUTPUT (SDIO)

3

Logic 1 Voltage (I

OH

= 800 μA) Full 1.79 V

Logic 0 Voltage (I

OL

= 50 μA) Full 0.05 V

DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644

Logic Compliance LVDS

Differential Output Voltage (V

OD

) Full ±290 ±345 ±400 mV

Output Offset Voltage (V

OS

) Full 1.15 1.25 1.35 V

Output Coding (Default) Twos complement

DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER,

REDUCED SIGNAL OPTION

Logic Compliance LVDS

Differential Output Voltage (V

OD

) Full ±160 ±200 ±230 mV

Output Offset Voltage (V

OS

) Full 1.15 1.25 1.35 V

Output Coding (Default) Twos complement

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

This is specified for LVDS and LVPECL only.

3

This is specified for 13 SDIO/OLM pins sharing the same connection.

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