DDR PHY Interface Specification v2.1.1 - DDR1/2/3, LPDDR2 Support

需积分: 10 163 浏览量更新于2024-07-22 收藏 926KB PDF 举报

"DDRPHYInterface(DFI)Specification Version2.1.1" DDR PHY 接口规格说明书v2.1.1详细介绍了DDR1、DDR2和DDR3内存PHY层（物理层）的标准接口，并且它还支持LPDDR2（低功耗双倍数据速率同步动态随机存取内存）。该文档由Denali Software, Inc.发布，该公司是存储解决方案领域的知名提供商，专注于内存接口技术。这份规格书涵盖了从1995年至2010年的版权信息，并在多个日期进行了修订以适应DDR3内存的支持和改进。 DDR PHY接口（DFI）是连接控制器和PHY之间的关键通信通道，用于实现高性能内存系统的稳定运行。DFI规范的主要目标是定义一套通用的接口标准，使得内存控制器和PHY之间的交互更加标准化，简化设计流程，并提高系统的兼容性和可靠性。在DDR内存系统中，PHY层负责与内存模块进行物理层面的数据传输，包括信号的发送、接收、时钟恢复等。DFI接口则提供了一种方法，让控制器可以控制PHY的某些关键功能，如时钟管理、命令与地址的传输、读写 leveling、数据眼图训练等。版本2.0的重大更新主要是为了支持DDR3内存，包括： 1. 添加了对DDR3内存特性的修改和补充，使其能够处理更高的数据速率和更复杂的内存操作。 2. 引入了读写leveling功能，这是DDR3内存中重要的校准过程，确保数据在传输过程中的精确时序对齐。 3. 删除了对PHY评估模式下数据眼图训练的引用，增加了针对gate训练的特定模式信号。 4. 对read leveling进行了修正和澄清，确保正确理解读取操作的校准过程。 5. 对表述进行了修改，统一了图示中的符号表示，进一步明确了读写leveling的术语。随着DDR内存技术的发展，DFI接口规格的不断更新和优化，为内存控制器和PHY之间提供了更为高效和可靠的通信方式，从而确保了整个系统的高性能和稳定性。这一规格不仅适用于新的系统设计，也是现有设计升级到更高内存标准的重要参考。

Interface Signal Groups

16 of 102 Denali Software DDR PHY Interface (DFI) Specification, Version 2.1

Denali Software, Inc.

More information on the write data interface is provided in Section 4.3, “Write

Transactions”. The signals and parameter in the write data interface are listed in Table 4

and Table 5.

TABLE 4. Write Data Signals

Signal From Width Default Description

dfi_wrdata

or dfi_wrdata_pN

MC DFI Data

Width

a. This signal is not meaningful during initialization. Therefore, no default value is required to be maintained for this signal.

Write data bus. The write data stream must begin t

phy_wrdata

cycles

after the dfi_wrdata_en signal is asserted for the number of cycles

that the dfi_wrdata_en signal is asserted.

For frequency ratio systems, the write data bus will be replicated

into phase-specific dfi_wrdata_pN buses that define the write data

for each phase N of the PHY clock.

dfi_wrdata_en

or dfi_wrdata_en_pN

MC DFI Data

Enable

Width

b. Since all bits of the dfi_wrdata_en signal are identical, the width of the signal on the MC side and the PHY side may be

different; the PHY is not required to use all of the bits.

0x0 Write data and data mask enable. These signals must be asserted

phy_wrdata

cycles before the data and data mask are sent on the

DFI interface. The dfi_wrdata_en signal must be sent t

phy_wrlat

cycles after the write command.

Once the dfi_wrdata_en signal is asserted, it must remain asserted

for the number of contiguous cycles of write data passed through

the DFI write data interface.

The width of the dfi_wrdata_en signal is defined as a DFI term.

Ideally, there will be a single dfi_wrdata_en bit for each slice of

memory data. The dfi_wrdata_en [0] signal corresponds with the

lowest segment of dfi_wrdata signals.

For frequency ratio systems, the write data enable signals will be

replicated into phase-specific dfi_wrdata_en_pN signals that

define the validity of write data for each phase N of the PHY clock.

dfi_wrdata_mask

or dfi_wrdata_mask_pN

MC DFI Data

Width / 8

Write data byte mask. The timing is the same as for the dfi_wrdata

bus. The dfi_wrdata_mask [0] signal defines masking for the

dfi_wrdata [7:0] signals, the dfi_wrdata_mask [1] signal defines

masking for the dfi_wrdata [15:8] signals, etc. If the dfi_wrdata

bus is not a multiple of 8, then the uppermost bit of the

dfi_wrdata_mask signal corresponds to the most significant

partial byte of data.

For frequency ratio systems, the write data mask bus will be

replicated into phase-specific dfi_wrdata_mask_pN buses that

define the write data masking information for each phase N of the

PHY clock.

Interface Signal Groups

Denali Software DDR PHY Interface (DFI) Specification, Version 2.1 17 of 102

Denali Software, Inc.

3.3 Read Data Interface

The read data interface handles the return of read data across the DFI. The read

mechanism defined by the DFI includes signal definitions along with timing

relationships defined by DFI timing parameters. The signals dfi_rddata,

dfi_rddata_en, dfi_rddata_valid, the LPDDR2 signal dfi_rddata_dnv, along with the

related timing parameters t

rddata_en

and t

phy_rdlat

are described in Table 6 and Table 7.

The dfi_rddata_en signal is asserted t

rddata_en

cycles after a read command is asserted

on the DFI control interface and must remain asserted for the number of contiguous

cycles that read data is expected. One continuous assertion of the dfi_rddata_en signal

may encompass data for multiple read commands. The dfi_rddata_en signal de-asserts

to signify there is no more contiguous data expected from the DFI read command(s).

Note that the dfi_rddata_en signal is not required to be asserted for any fixed number

of cycles.

TABLE 5. Write Data Timing Parameters

Parameter

Defined

By Min Max Unit Description

phy_wrdata

PHY 0

a. The DFI does not specify a maximum value. The range of values supported is implementation-specific.

DFI PHY

clock

cycles

b. This timing parameter is defined in terms of DFI PHY clock cycles for frequency ratio systems. For matched frequency

systems, a DFI PHY clock is identical to the DFI clock.

Specifies the number of DFI PHY clock cycles between when the

dfi_wrdata_en signal is asserted to when the associated write data is

driven on the dfi_wrdata signal. This has no impact on performance,

only adjusts the relative time between enable and data transfer. DFI

1.0 and DFI 2.0 memory controllers will only support a t

phy_wrdata

value of 1. A PHY will generally be designed to operate at a single

phy_wrdata

value; however, the MC should support a range of values.

NOTE: This parameter may be specified as a fixed value, or as a

constant based on other fixed values in the system.

phy_wrdelay

PHY 0

1 or 3

c. The PHY must support a maximum write data delay of one less than the clock ratio. A 1:2 frequency ratio PHY must support

values of 0 and 1. A 1:4 frequency ratio PHY must support a range of 0-3.

DFI PHY

clock

cycles

Specifies the number of DFI PHY clock cycles of additional delay

that the PHY must insert between the write data enable and write

data once data has been captured from the DFI bus. This parameter is

only used in frequency ratio systems.

phy_wrlat

PHY 0

DFI PHY

clock

cycles

Specifies the number of DFI PHY clock cycles between when a write

command is sent on the DFI control interface and when the

dfi_wrdata_en signal is asserted.

NOTE: This parameter may be specified as a fixed value, or as a

constant based on other fixed values in the system.

Interface Signal Groups

18 of 102 Denali Software DDR PHY Interface (DFI) Specification, Version 2.1

Denali Software, Inc.

The t

rddata_en

parameter defines the timing requirements between the read command on

the DFI interface and the assertion of the dfi_rddata_en signal at the DFI boundary for

the start of contiguous read data expected on the DFI interface. The exact value of this

parameter for a particular application is determined by the components in the entire

DRAM system. The DFI specification does not dictate a value but does require that

once this value has been determined, the dfi_rddata_en signal must be asserted based

on this timing parameter.

The t

phy_rdlat

parameter defines the maximum number of cycles allowed from the

assertion of the dfi_rddata_en signal to the assertion of the dfi_rddata_valid signal.

This parameter is specified by the system, but the exact value of this parameter is not

determined by the DFI specification.

These timing parameters (t

rddata_en

and t

phy_rdlat

) must be held constant while

commands are being executed on the DFI bus; however, if necessary, these values may

be changed when the bus is idle. These parameters work together to define a maximum

number of cycles from the assertion of a read command on the DFI control interface to

the assertion of the dfi_rddata_valid signal, indicating the first valid data of the

contiguous read data. Read data may be returned earlier by asserting the

dfi_rddata_valid signal before t

phy_rdlat

cycles have expired. When the signal

dfi_rddata_valid is asserted, the entire DFI read data word must be valid. For the

LPDDR2 DFI, the signal dfi_rddata_dnv must also be sent with the read data signal

dfi_rddata when the dfi_rddata_valid signal is asserted.

For frequency ratio systems, the read data enable signal will be replicated into phase-

specific signals with a suffix of “_pN” that defines the signal value for each phase N of

the DFI PHY clock relative to the DFI clock. The read data, read data valid and read

data not valid signals will be replaced with DFI data word-specific signals with a suffix

of “_wN” with the DFI data word N. For all signal types, the suffix for phase 0/word 0

is optional.

More information on the read data interface is provided in Section 4.4, “Read

Transactions”. The signals and parameters in the read data interface are listed in Table 6

and Table 7.

TABLE 6. Read Data Signals

Signal From Width Default Description

dfi_rddata

or dfi_rddata_wN

PHY DFI Data

Width

Read data bus. Read data is expected to be received at the MC

within t

phy_rdlat

cycles after the dfi_rddata_en signal is asserted.

For frequency ratio systems, the read data bus will be replicated

into DFI data word-specific dfi_rddata_wN buses that define the

read data for each DFI data word. For a 1:2 frequency ratio system,

there are 2 dfi_rddata_wN signals. For a 1:4 frequency ratio

system, there are 4 dfi_rddata_wN signals.

Interface Signal Groups

Denali Software DDR PHY Interface (DFI) Specification, Version 2.1 19 of 102

Denali Software, Inc.

dfi_rddata_en

or dfi_rddata_en_pN

MC DFI Data

Enable

Width

0x0 Read data enable. The dfi_rddata_en signal must be asserted

rddata_en

cycles after the assertion of a read command on the DFI

control interface and remains valid for the duration of contiguous

read data expected on the dfi_rddata bus.

The width of the dfi_rddata_en signal is defined as a DFI term.

Ideally, there will be a single dfi_rddata_en bit for each slice of

memory data. The dfi_rddata_en [0] signal corresponds with the

lowest segment of dfi_rddata signals.

For frequency ratio systems, the read data enable signals will be

replicated into phase-specific dfi_rddata_en_pN signals that

define the read data enable for each phase N of the PHY clock.

dfi_rddata_valid

or dfi_rddata_valid_wN

PHY DFI Read

Data Valid

Width

0x0 Read data valid indicator. The dfi_rddata_valid signal will be

asserted with the read data for the number of cycles that data is

being sent. The timing is the same as for the dfi_rddata bus.

For frequency ratio systems, the read data valid signals will be

replicated into DFI data word-specific dfi_rddata_valid_wN

signals that define the validity of the read data. For a 1:2 frequency

ratio system, there are 2 dfi_rddata_valid_wN signals. For a 1:4

frequency ratio system, there are 4 dfi_rddata_valid_wN signals.

dfi_rddata_dnv

or dfi_rddata_dnv_wN

PHY DFI Data

Width / 8

0x0 DFI data not valid. The timing is the same as for the

dfi_rddata_valid signal.

The dfi_rddata_dnv [0] signal correlates to the dfi_rddata [7:0]

signals, the dfi_rddata_dnv [1] signal correlates to the dfi_rddata

[15:8] signals, etc. If the dfi_rddata bus is not a multiple of 8, then

the uppermost bit of the dfi_rddata_dnv signal corresponds to the

most significant partial byte of data.

For frequency ratio systems, the read data not valid signals will be

replicated into DFI data word-specific dfi_rddata_dnv_wN

signals that define the validity of read data. For a 1:2 frequency

ratio system, there are 2 dfi_rddata_dnv_wN signals. For a 1:4

frequency ratio system, there are 4 dfi_rddata_dnv_wN signals.

This signal is only required for DFI LPDDR2 support.

a. This signal is not meaningful during initialization. Therefore, no default value is required to be maintained for this signal.

b. Since all bits of the dfi_rddata_en signal are identical, the width of the signal on the MC side and the PHY side may be

different; the PHY is not required to use all of the bits.

c. Since all bits of the dfi_rddata_valid signal are identical, the width of the signal on the MC side and the PHY side may be

different; the MC is not required to use all of the bits.

TABLE 6. Read Data Signals

Signal From Width Default Description

Interface Signal Groups

20 of 102 Denali Software DDR PHY Interface (DFI) Specification, Version 2.1

Denali Software, Inc.

3.4 Update Interface

During system operation, the system may require updates to internal settings to

compensate for environmental conditions. To ensure that updates do not interfere with

signals on the DRAM interface, the DFI supports update modes where the DFI read,

write, and control interface are suspended from normal activity. The DFI specification

supports both MC-initiated and PHY-initiated updates. More information on the update

interface is provided in Section 4.5, “PHY Update”.

If a MC initiates an update request by asserting the dfi_ctrlupd_req signal, the request

can be acknowledged or ignored by the PHY. If the request is acknowledged by

asserting the dfi_ctrlupd_ack signal, the protocol described in Section 4.5.1, “MC-

Initiated Update” must be followed. The DFI specification requires the MC to issue

update requests and it specifies a maximum interval (t

ctrlupd_interval

)

at which requests

must be offered. The MC must assert the dfi_ctrlupd_req signal at the end of memory

initialization, including all required training routines, to signify that the initialization is

complete.

If a PHY initiates an update request by asserting the dfi_phyupd_req signal, the request

must be acknowledged by the MC through a dfi_phyupd_ack signal assertion. The DFI

specifies up to 4 different update PHY-initiated request modes. Each mode differs only

in the number of cycles that the DFI interface must be suspended while the update

occurs. During this time, the MC is responsible for placing the system in a state where

the DFI bus is suspended from all activity other than activity specifically related to the

update process being executed. Refer to Section 4.5.2, “PHY-Initiated Update” for more

details on this protocol. The DFI specification does not require the PHY to issue update

TABLE 7. Read Data Timing Parameters

Parameter

Defined

By Min Max Unit Description

phy_rdlat

PHY 0

a. The DFI does not specify a maximum value. The range of values supported is implementation-specific.

DFI PHY

clock

cycles

b. This timing parameter is defined in terms of DFI PHY clock cycles for frequency ratio systems. For matched frequency

systems, a DFI PHY clock is identical to the DFI clock.

Specifies the maximum number of DFI PHY clock cycles allowed

from the assertion of the dfi_rddata_en signal to the assertion of the

dfi_rddata_valid signal.

NOTE: This parameter may be specified as a fixed value, or as a

constant based on other fixed values in the system.

rddata_en

System 0

DFI PHY

clock

cycles

Specifies the number of DFI PHY clock cycles from the assertion of

a read command on the DFI to the assertion of the dfi_rddata_en

signal.

NOTE: This parameter may be specified as a fixed value, or as a

constant based on other fixed values in the system.

剩余101页未读，继续阅读

shangang

粉丝: 1
资源: 1

DDR PHY Interface Specification v2.1.1 - DDR1/2/3, LPDDR2 Suppor...

最新资源

DDR PHY Interface Specification v2.1.1 - DDR1/2/3, LPDDR2 Suppor...

DDR_PHY_Interface_Specification_v5_0.pdf

DDR_PHY_Interface_Specification_v3_0.pdf

eetop.cn_DDR_PHY_Interface_Specification__v3_0.pdf

eetop.cn_DDR_PHY_Interface_Specification_v4_0.rar_DDR_PHY_Interf

DDR_PHY_Interface_Specification_v3_1

DDR_PHY_Interface_Specification_v5_1.pdf

DDR_PHY_Interface_Specification_v4_02.pdf

DDR_PHY_Interface_Specification_v4_0.pdf

ddr_for_controller_and_phy_ddrphy_ddr_chargeone_fpgaphy_ddr_cont

easic-ips-01-n3x_ddr3_phy.zip_PHY_ddr3_ddr3 phy_phy ddr3

最新资源