"ARM v9系统架构手册：权威指南及最新信息"

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The Arm Architecture Reference Manual v9 is the latest manual for the ARMv9 system architecture. This comprehensive guide is essential for understanding the intricacies of the Arm A-profile architecture. The manual, copyrighted by Arm Limited and its affiliates, provides detailed information on the design and functionality of the Arm processors. The Arm Architecture Reference Manual covers a wide range of topics, including instruction sets, memory management, system control, and security features. It serves as a valuable resource for software developers, system designers, and anyone working with Arm-based technologies. The manual is designed to help users optimize the performance and efficiency of their systems while maintaining compatibility with the Arm architecture standards. The Armv9 system architecture introduces new features and improvements over its predecessors, offering enhanced performance, security, and scalability. With the advancements in technology and the increasing complexity of modern systems, the Arm Architecture Reference Manual v9 is indispensable for staying current with the latest developments in the Arm ecosystem. In addition to providing technical specifications and architectural details, the manual also includes release information and proprietary notices. It is a non-confidential document that allows users to delve into the inner workings of the Arm A-profile architecture without any restrictions. Overall, the Arm Architecture Reference Manual v9 is a comprehensive and authoritative guide that reflects the cutting-edge advancements in Arm processor technology. It is a must-have resource for anyone seeking to understand and leverage the power of Arm-based systems for their applications.

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Preface

About this Manual

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About this Manual

This Manual describes the Arm

architecture v8, Armv8, and the Arm

architecture v9, Armv9. The architecture

describes the operation of an Armv8-A and an Armv9-A Processing element (PE), and this Manual includes

descriptions of:

• The two Execution states, AArch64 and AArch32.

• The instruction sets:

— In AArch32 state, the A32 and T32 instruction sets, which are compatible with earlier versions of the

Arm architecture.

— In AArch64 state, the A64 instruction set.

• The states that determine how a PE operates, including the current Exception level and Security state, and in

AArch32 state the PE mode.

• The Exception model.

• The interprocessing model, that supports transitioning between AArch64 state and AArch32 state.

• The memory model, that defines memory ordering and memory management. This Manual covers the Arm

A architecture profile, both Armv8-A and Armv9-A, that defines a Virtual Memory System Architecture

(VMSA).

• The programmers’ model, and its interfaces to System registers that control most PE and memory system

features, and provide status information.

• The Advanced SIMD and floating-point instructions, which provide high-performance:

— Single-precision, half-precision, and double-precision floating-point operations.

— Conversions between double-precision, single-precision, and half-precision floating-point values.

— Integer, single-precision floating-point, and half-precision floating-point vector operations in all

instruction sets.

— Double-precision floating-point vector operations in the A64 instruction set.

• The security model, which provides two Security states to support Secure applications.

• The virtualization model.

• The Debug architecture, which provides software access to debug features.

This Manual gives the assembler syntax for the instructions it describes, meaning that it describes instructions in

textual form. However, this Manual is not a tutorial for Arm assembler language, nor does it describe Arm assembler

language, except at a very basic level. To make effective use of Arm assembler language, read the documentation

supplied with the assembler being used.

This Manual is organized into parts:

Part A Provides an introduction to the Arm architecture, and an overview of the AArch64 and AArch32

Execution states.

Part B Describes the application level view of the AArch64 Execution state, meaning the view from EL0.

It describes the application level view of the programmers’ model and the memory model.

Part C Describes the A64 instruction set, which is available in the AArch64 Execution state. The

descriptions for each instruction also include the precise effects of each instruction when executed

at EL0, described as unprivileged execution, including any restrictions on its use, and how the

effects of the instruction differ at higher Exception levels. This information is of primary importance

to authors and users of compilers, assemblers, and other programs that generate Arm machine code.

Part D Describes the system level view of the AArch64 Execution state. It includes details of the System

registers, most of which are not accessible from EL0, and the system level view of the programmers’

model and the memory model. This part includes the description of self-hosted debug.

Preface

About this Manual

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Part E Describes the application level view of the AArch32 Execution state, meaning the view from the

EL0. It describes the application level view of the programmers’ model and the memory model.

Note

In AArch32 state, execution at EL0 is execution in User mode.

Part F Describes the T32 and A32 instruction sets, which are available in the AArch32 Execution state.

These instruction sets are backwards-compatible with earlier versions of the Arm architecture. This

part describes the precise effects of each instruction when executed in User mode, described as

unprivileged execution or execution at EL0, including any restrictions on its use, and how the effects

of the instruction differ at higher Exception levels. This information is of primary importance to

authors and users of compilers, assemblers, and other programs that generate Arm machine code.

Note

User mode is the only mode where software execution is unprivileged.

Part G Describes the system level view of the AArch32 Execution state, which is generally compatible with

earlier versions of the Arm architecture. This part includes details of the System registers, most of

which are not accessible from EL0, and the instruction interface to those registers. It also describes

the system level view of the programmers’ model and the memory model.

Part H Describes the Debug architecture for external debug. This provides configuration, breakpoint and

watchpoint support, and a Debug Communications Channel (DCC) to a debug host.

Part I Describes additional features of the architecture that are not closely coupled to a processing element

(PE), and therefore are accessed through memory-mapped interfaces. Some of these features are

OPTIONAL.

Part J Provides pseudocode that describes various features of the Arm architecture.

Part K, Appendixes

Provide additional information. Some appendixes give information that is not part of the Armv8 or

Armv9 architectural requirements. The cover page of each appendix indicates its status.

Glossary Defines terms used in this Manual that have a specialized meaning.

Note

Terms that are generally well understood in the microelectronics industry are not included in the

Glossary.

Preface

Using this Manual

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Using this Manual

The information in this Manual is organized into parts, as described in this section.

Part A, Introduction and Architecture Overview

Part A gives an overview of the Armv8-A and Armv9-A architecture profiles, including its relationship to the other

Arm PE architectures. It introduces the terminology used to describe the architecture, and gives an overview of the

Executions states, AArch64 and AArch32. It contains the following chapters:

Chapter A1 Introduction to the Arm Architecture

Read this for an introduction to the Arm architecture.

Chapter A2 Armv8-A Architecture Extensions

Read this for an introduction to the Armv8 architecture extensions.

Chapter A3 Armv9 Architecture Extensions

Read this for an introduction to the Armv9 architecture extensions.

Part B, The AArch64 Application Level Architecture

Part B describes the AArch64 state application level view of the architecture. It contains the following chapters:

Chapter B1 The AArch64 Application Level Programmers’ Model

Read this for an application level description of the programmers’ model for software executing in

AArch64 state. It describes execution at EL0 when EL0 is using AArch64 state.

Chapter B2 The AArch64 Application Level Memory Model

Read this for an application level description of the memory model for software executing in

AArch64 state. It describes the memory model for execution in EL0 when EL0 is using AArch64

state. It includes information about Arm memory types, attributes, and memory access controls.

Part C, The A64 Instruction Set

Part C describes the A64 instruction set, which is used in AArch64 state. It contains the following chapters:

Chapter C1 The A64 Instruction Set

Read this for a description of the A64 instruction set and common instruction operation details.

Chapter C2 About the A64 Instruction Descriptions

Read this to understand the format of the A64 instruction descriptions.

Chapter C3 A64 Instruction Set Overview

Read this for an overview of the A64 instructions.

Chapter C4 A64 Instruction Set Encoding

Read this for a description of the A64 instruction set encoding.

Chapter C5 The A64 System Instruction Class

Read this for a description of the AArch64 System instructions and register descriptions, and the

System instruction class encoding space.

Chapter C6 A64 Base Instruction Descriptions

Read this for information on key aspects of the A64 base instructions and for descriptions of the

individual instructions, which are listed in alphabetical order.

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