Cortex-A8 技术参考手册 r3p2：ARM 架构解析

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"Cortex-A8 技术参考手册 r3p2" 《Cortex-A8 技术参考手册 r3p2》是ARM Limited发布的一份详细的技术文档，主要针对TI（Texas Instruments）达芬奇平台经常使用的技术进行阐述。这份手册的版权归属ARM Limited，版本号为r3p2，其内容涵盖自2006年至2009年的更新。DDI0344J是手册的识别编号，表明这是一份关于非机密且无限制访问的Cortex-A8处理器的技术参考资料。 Cortex-A8是ARM架构中的一款高性能处理器核心，广泛应用于移动设备、嵌入式系统和数字信号处理等领域。该技术参考手册提供了Cortex-A8核心的详细规格、功能、指令集、性能优化建议以及硬件接口等信息。在手册的修订信息中，提到了自发布以来的变更，但具体的变更内容没有在此段落中给出。此外，手册中还包含了ARM公司及其它相关品牌的商标声明，强调未经版权所有者书面许可，不得改编或复制其中的信息，同时指出产品描述可能随着持续发展和改进而发生变化。手册提供的信息是ARM公司在诚信基础上提供的，但不提供任何明示或暗示的保证。这意味着用户在使用手册时应理解，尽管手册内容详尽，但实际产品的具体细节和使用可能会有所变化，用户需要根据最新的技术更新和产品说明进行操作。 Cortex-A8的技术特性包括先进的微体系结构，支持乱序执行、多线程、硬件浮点运算单元（FPU）、NEON媒体处理引擎，以及高效的电源管理等功能。这些特性使得Cortex-A8在处理复杂的计算任务、多媒体应用和移动设备上的性能表现突出。通过这份手册，开发者和工程师可以深入理解Cortex-A8的内部工作原理，学习如何利用其特性进行软件开发和系统设计，以实现最佳的性能和能效。同时，手册还可能包含调试工具的使用指南、异常处理机制、内存系统设计以及兼容性方面的信息，这些都是开发基于Cortex-A8平台的系统所必需的关键知识。总而言之，《Cortex-A8 技术参考手册 r3p2》是开发、优化和维护基于Cortex-A8处理器的系统的重要参考资料，它为工程师提供了深入的技术洞察，帮助他们充分利用这个强大处理器的能力。

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Table 11-19 Summary of MBIST patterns ................................................................................ 11-25

Table 12-1 Access to CP14 debug registers ............................................................................ 12-7

Table 12-2 CP14 debug registers summary ............................................................................. 12-8

Table 12-3 Debug memory-mapped registers .......................................................................... 12-9

Table 12-4 Processor reset effect on debug and ETM logic ................................................... 12-12

Table 12-5 APB interface access with relation to software lock ............................................. 12-14

Table 12-6 Debug registers access with relation to power-down event .................................. 12-15

Table 12-7 Power management registers access with relation to power-down event ............ 12-15

Table 12-8 ETM and CTI registers access with relation to power-down event ....................... 12-16

Table 12-9 Terms used in register descriptions ...................................................................... 12-17

Table 12-10 CP14 debug registers ........................................................................................... 12-17

Table 12-11 Debug ID Register bit functions ............................................................................ 12-19

Table 12-12 Debug ROM Address Register bit functions ......................................................... 12-20

Table 12-13 Debug Self Address Offset Register bit functions ................................................. 12-21

Table 12-14 Debug Status and Control Register bit functions .................................................. 12-23

Table 12-15 Data Transfer Register bit functions ..................................................................... 12-30

Table 12-16 Watchpoint Fault Address Register bit functions .................................................. 12-30

Table 12-17 Vector Catch Register bit functions ...................................................................... 12-32

Table 12-18 Event Catch Register bit functions ........................................................................ 12-34

Table 12-19 Debug State Cache Control Register bit functions ............................................... 12-35

Table 12-20 Instruction Transfer Register bit functions ............................................................ 12-36

Table 12-21 Debug Run Control Register bit functions ............................................................ 12-37

Table 12-22 Breakpoint Value Registers bit functions .............................................................. 12-38

Table 12-23 Breakpoint Control Registers bit functions ............................................................ 12-39

Table 12-24 Meaning of BVR bits [22:20] ................................................................................. 12-41

Table 12-25 Watchpoint Value Registers bit functions ............................................................. 12-42

Table 12-26 Watchpoint Control Registers bit functions ........................................................... 12-44

Table 12-27 OS Lock Access Register bit functions ................................................................. 12-47

Table 12-28 OS Lock Status Register bit functions .................................................................. 12-48

Table 12-29 OS Save and Restore Register bit functions ........................................................ 12-49

Table 12-30 PRCR bit functions ............................................................................................... 12-51

Table 12-31 PRSR bit functions ................................................................................................ 12-52

Table 12-32 Management registers .......................................................................................... 12-54

Table 12-33 Processor Identifier Registers ............................................................................... 12-55

Table 12-34 Integration Internal Output Control Register bit functions ..................................... 12-57

Table 12-35 Integration External Output Control Register bit functions .................................... 12-59

Table 12-36 Integration Input Status Register bit functions ...................................................... 12-60

Table 12-37 Integration Mode Control Register bit functions .................................................... 12-61

Table 12-38 Claim Tag Set Register bit functions .................................................................... 12-62

Table 12-39 Claim Tag Clear Register bit functions ................................................................. 12-62

Table 12-40 Lock Access Register bit functions ....................................................................... 12-63

Table 12-41 Lock Status Register bit functions ........................................................................ 12-64

Table 12-42 Authentication Status Register bit functions ......................................................... 12-65

Table 12-43 Device Type Register bit functions ....................................................................... 12-66

Table 12-44 Peripheral Identification Registers ........................................................................ 12-66

Table 12-45 Fields in the Peripheral Identification Registers .................................................... 12-67

Table 12-46 Peripheral ID Register 0 bit functions ................................................................... 12-67

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Table 12-47 Peripheral ID Register 1 bit functions .................................................................... 12-68

Table 12-48 Peripheral ID Register 2 bit functions .................................................................... 12-68

Table 12-49 Peripheral ID Register 3 bit functions .................................................................... 12-68

Table 12-50 Peripheral ID Register 4 bit functions .................................................................... 12-69

Table 12-51 Component Identification Registers ...................................................................... 12-69

Table 12-52 Processor behavior on debug events .................................................................... 12-72

Table 12-53 Values in Link Register after exceptions ............................................................... 12-75

Table 12-54 Read PC value after debug state entry ................................................................. 12-79

Table 12-55 Permitted updates to the CPSR in debug state .................................................... 12-82

Table 12-56 Accesses to CP15 and CP14 registers in debug state ......................................... 12-83

Table 12-57 Authentication signal restrictions ........................................................................... 12-91

Table 12-58 Values to write to BCR for a simple breakpoint ..................................................... 12-98

Table 12-59 Values to write to WCR for a simple watchpoint ................................................. 12-100

Table 12-60 Example byte address masks for watchpointed objects ..................................... 12-101

Table 13-1 Single-precision three-operand register usage ..................................................... 13-10

Table 13-2 Single-precision two-operand register usage ........................................................ 13-11

Table 13-3 Double-precision three-operand register usage .................................................... 13-11

Table 13-4 Double-precision two-operand register usage ...................................................... 13-11

Table 13-5 NEON and VFP system registers .......................................................................... 13-12

Table 13-6 Accessing NEON and VFP system registers ........................................................ 13-12

Table 13-7 FPSID Register bit functions ................................................................................. 13-14

Table 13-8 FPSCR Register bit functions ............................................................................... 13-15

Table 13-9 Vector length and stride combinations .................................................................. 13-17

Table 13-10 Floating-Point Exception Register bit functions ..................................................... 13-18

Table 13-11 MVFR0 Register bit functions ............................................................................... 13-19

Table 13-12 MVFR1 Register bit functions ............................................................................... 13-20

Table 13-13 Default NaN values ............................................................................................... 13-23

Table 13-14 QNaN and SNaN handling .................................................................................... 13-24

Table 14-1 ETM implementation ............................................................................................... 14-6

Table 14-2 ETM register summary ............................................................................................ 14-8

Table 14-3 ID Register bit functions ........................................................................................ 14-11

Table 14-4 Configuration Code Register bit functions ............................................................. 14-12

Table 14-5 Configuration Code Extension Register bit functions ............................................ 14-13

Table 14-6 Peripheral Identification Registers bit functions .................................................... 14-14

Table 14-7 Component Identification Registers bit functions .................................................. 14-16

Table 14-8 Output signals that can be controlled by the Integration Test Registers ............... 14-17

Table 14-9 Input signals that can be read by the Integration Test Registers .......................... 14-17

Table 14-10 ITMISCOUT Register bit functions ........................................................................ 14-18

Table 14-11 ITMISCIN Register bit functions ............................................................................ 14-19

Table 14-12 ITTRIGGER Register bit functions ........................................................................ 14-19

Table 14-13 ITATBDATA0 Register bit functions ...................................................................... 14-20

Table 14-14 ITATBCTR2 Register bit functions ........................................................................ 14-21

Table 14-15 ITATBCTR1 Register bit functions ........................................................................ 14-21

Table 14-16 ITATBCTR0 Register bit functions ........................................................................ 14-22

Table 14-17 PMU event number mappings ............................................................................... 14-32

Table 14-18 PMU event cycle mappings ................................................................................... 14-34

Table 15-1 Trigger inputs .......................................................................................................... 15-6

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Table 15-2 Trigger outputs ........................................................................................................ 15-6

Table 15-3 CTI register summary ........................................................................................... 15-10

Table 15-4 CTI Control Register bit functions ......................................................................... 15-13

Table 15-5 CTI Interrupt Acknowledge Register bit functions ................................................. 15-14

Table 15-6 CTI Application Trigger Set Register bit functions ................................................ 15-15

Table 15-7 CTI Application Trigger Clear Register bit functions ............................................. 15-16

Table 15-8 CTI Application Pulse Register bit functions ......................................................... 15-16

Table 15-9 CTI Trigger to Channel Enable Registers bit functions ......................................... 15-17

Table 15-10 CTI Channel to Trigger Enable Registers bit functions ......................................... 15-18

Table 15-11 CTI Trigger In Status Register bit functions .......................................................... 15-19

Table 15-12 CTI Trigger Out Status Register bit functions ....................................................... 15-19

Table 15-13 CTI Channel In Status Register bit functions ........................................................ 15-20

Table 15-14 CTI Channel Gate Register bit functions .............................................................. 15-21

Table 15-15 ASIC Control Register bit functions ...................................................................... 15-22

Table 15-16 CTI Channel Out Status Register bit functions ..................................................... 15-23

Table 15-17 CTI Integration Test Registers .............................................................................. 15-24

Table 15-18 ITTRIGINACK Register bit functions .................................................................... 15-25

Table 15-19 ITCHOUT Register bit functions ........................................................................... 15-25

Table 15-20 ITTRIGOUT Register bit functions ........................................................................ 15-26

Table 15-21 ITTRIGOUT connections to other integration test registers .................................. 15-26

Table 15-22 ITTRIGOUTACK Register bit functions ................................................................ 15-27

Table 15-23 ITTRIGOUTACK connections to other integration test registers .......................... 15-27

Table 15-24 ITCHIN Register bit functions ............................................................................... 15-28

Table 15-25 ITTRIGIN Register bit functions ............................................................................ 15-28

Table 15-26 ITTRIGIN connections to other integration test registers ...................................... 15-29

Table 15-27 Authentication Status Register bit functions ......................................................... 15-30

Table 15-28 Device ID Register bit functions ............................................................................ 15-30

Table 15-29 Device Type Identifier Register bit functions ........................................................ 15-31

Table 15-30 Peripheral Identification Registers bit functions .................................................... 15-31

Table 15-31 Component Identification Registers bit functions .................................................. 15-33

Table 16-1 Data-processing instructions with a destination ...................................................... 16-5

Table 16-2 Data-processing instructions without a destination ................................................. 16-6

Table 16-3 MOV and MOVN instructions .................................................................................. 16-6

Table 16-4 Multiply instructions ................................................................................................ 16-7

Table 16-5 Parallel arithmetic instructions ................................................................................ 16-8

Table 16-6 Extended instructions ............................................................................................. 16-8

Table 16-7 Miscellaneous data-processing instructions ........................................................... 16-8

Table 16-8 Status register access instructions ......................................................................... 16-9

Table 16-9 Load instructions ..................................................................................................... 16-9

Table 16-10 Store instructions .................................................................................................. 16-10

Table 16-11 Branch instructions ............................................................................................... 16-12

Table 16-12 Nonpipelined CP14 instructions ............................................................................ 16-12

Table 16-13 Nonpipelined CP15 instructions ............................................................................ 16-13

Table 16-14 CP15 instructions affected when ACTRL bit[20] = 0 ............................................ 16-15

Table 16-15 Dual-issue restrictions .......................................................................................... 16-16

Table 16-16 Memory system effects on instruction timings ...................................................... 16-18

Table 16-17 ThumbEE instructions ........................................................................................... 16-19

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Table 16-18 Advanced SIMD integer ALU instructions ............................................................. 16-25

Table 16-19 Advanced SIMD integer multiply instructions ........................................................ 16-28

Table 16-20 Advanced SIMD integer shift instructions ............................................................. 16-31

Table 16-21 Advanced SIMD floating-point instructions ........................................................... 16-32

Table 16-22 Advanced SIMD byte permute instructions ........................................................... 16-34

Table 16-23 Advanced SIMD load/store instructions ................................................................ 16-36

Table 16-24 Advanced SIMD register transfer instructions ....................................................... 16-43

Table 16-25 VFP Instruction cycle counts ................................................................................. 16-45

Table 17-1 Format of timing parameter tables .......................................................................... 17-3

Table 17-2 Timing parameters of AXI interface ......................................................................... 17-4

Table 17-3 Timing parameters of ATB and CTI interfaces ........................................................ 17-6

Table 17-4 Timing parameters of APB interface and miscellaneous debug signals ................. 17-7

Table 17-5 Timing parameters of the L1 and L2 MBIST interface ............................................ 17-9

Table 17-6 Timing parameters of the L2 preload interface ..................................................... 17-10

Table 17-7 Timing parameters of the DFT interface ............................................................... 17-11

Table 17-8 Timing parameters of miscellaneous signals ........................................................ 17-12

Table A-1 AXI interface .............................................................................................................. A-2

Table A-2 ATB interface ............................................................................................................ A-3

Table A-3 MBIST interface ........................................................................................................ A-4

Table A-4 DFT and additional MBIST pin requirements ............................................................ A-5

Table A-5 Preload engine interface ........................................................................................... A-7

Table A-6 APB interface ............................................................................................................ A-8

Table A-7 Miscellaneous signals ............................................................................................. A-10

Table A-8 Miscellaneous debug signals .................................................................................. A-14

Table A-9 Miscellaneous ETM and CTI signals ....................................................................... A-17

Table B-1 Advanced SIMD mnemonics ..................................................................................... B-2

Table B-2 VFP data-processing mnemonics ............................................................................. B-5

Table C-1 Differences between issue F and issue G ................................................................ C-1

Table C-2 Differences between issue G and issue H ............................................................... C-2

Table C-3 Differences between issue H and issue I ................................................................. C-3

Table C-4 Differences between Issue I and Issue J ................................................................. C-4

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