MPC8548EEC CPU技术规格与功能详解

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"MPC8548EEC-1127170是一款由Freescale Semiconductor生产的CPU，详细介绍了其各项功能和性能。这款CPU属于PowerQUICC III系列，适用于高性能的嵌入式应用。文档包含了从概述到具体功能模块的详细信息，如电气特性、电源特性、输入时钟、重置初始化、DDR和DDR2 SDRAM接口、DUART、增强型三速以太网(eTSEC)、以太网管理接口、局部总线和可编程中断控制器等。" 本文档是关于Freescale Semiconductor的MPC8548EEC-1127170 CPU的技术数据手册，旨在提供全面的设备特性和操作指南。CPU的总体概述中提到了它主要的功能单元，包括但不限于处理器核心、内存接口、网络控制器、串行通信和其他外设接口。MPC8548E家族还包括MPC8547E、MPC8545E和MPC8543E，它们之间可能存在一些差异，如引脚布局和处理器频率范围，这些差异在文档中会特别指出。在电气特性章节，用户可以了解到该CPU的工作电压、电流消耗以及各种工作模式下的功耗等关键信息，这对于系统设计和散热管理至关重要。电源特性部分详细描述了CPU在不同状态下的电源需求，包括启动、运行和待机模式。输入时钟章节则关注于CPU如何处理外部时钟源，这对于系统的时序管理和同步至关重要。RESET初始化部分详细说明了如何正确地复位和初始化CPU，以确保稳定的操作。对于内存部分，文档涵盖了DDR和DDR2 SDRAM的接口规格，包括时序参数和信号电平，这对于选择合适的内存组件和实现高效的内存访问至关重要。 DUART（双通用异步接收器/发送器）部分提供了串行通信的详细信息，通常用于系统与外部设备的串行接口。增强型三速以太网(eTSEC)功能支持千兆以太网连接，具有高级的网络特性，如流量控制和错误检测。此外，文档还涵盖了以太网管理接口的电气特性，以便进行网络配置和监控。局部总线部分详细阐述了CPU与外部设备之间的高速数据传输，而可编程中断控制器则描述了CPU如何管理和响应来自不同源的中断请求，这是实时系统响应性能的关键。这份文档为设计者提供了全面了解和使用MPC8548EEC-1127170 CPU所需的所有基本信息，是开发基于该处理器的嵌入式系统的重要参考资料。

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10

16 Freescale Semiconductor

Input Clocks

4 Input Clocks

This section discusses the timing for the input clocks.

4.1 System Clock Timing

The following table provides the system clock (SYSCLK) AC timing specifications for the device.

4.2 Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then

used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter

specification. The minimum pulse width of the RTC signal must be greater than 2x the period of the CCB

clock. That is, minimum clock high time is 2 × t

CCB

, and minimum clock low time is 2 × t

CCB

. There is

no minimum RTC frequency; RTC may be grounded if not needed.

Table 5. SYSCLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OV

= 3.3 V ± 165 mV.

Parameter/Condition Symbol Min Typ Max Unit Notes

SYSCLK frequency f

SYSCLK

16 — 133 MHz 1, 6, 7, 8

SYSCLK cycle time t

SYSCLK

7.5 — 60 ns 6, 7, 8

SYSCLK rise and fall time t

, t

0.6 1.0 1.2 ns 2

SYSCLK duty cycle t

KHK

SYSCLK

40 — 60 % 3

SYSCLK jitter — — — ±150 ps 4, 5

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies.See Section 20.2, “CCB/SYSCLK PLL Ratio,” and Section 20.3, “e500 Core PLL Ratio,” for ratio

settings.

2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth must be <500 kHz at –20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

6. This parameter has been adjusted slower according to the workaround for device erratum GEN 13.

7. For spread spectrum clocking. Guidelines are + 0% to –1% down spread at modulation rate between 20 and 60 kHz on

SYSCLK.

8. System with operating core frequency less than 1200 MHz must limit SYSCLK frequency to 100 MHz maximum.

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor 17

Input Clocks

4.3 eTSEC Gigabit Reference Clock Timing

The following table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing

specifications for the device.

4.4 PCI/PCI-X Reference Clock Timing

When the PCI/PCI-X controller is configured for asynchronous operation, the reference clock for the

PCI/PCI-x controller is not the SYSCLK input, but instead the PCIn_CLK. The following table provides

the PCI/PCI-X reference clock AC timing specifications for the device.

Table 6. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit Notes

EC_GTX_CLK125 frequency f

G125

—125—MHz—

EC_GTX_CLK125 cycle time t

G125

—8—ns

EC_GTX_CLK125 rise and fall time

L/TVDD = 2.5 V

L/TVDD = 3.3 V

G125R

, t

G125F

——

0.75

1.0

ns 1

EC_GTX_CLK125 duty cycle

GMII, TBI

1000Base-T for RGMII, RTBI

G125H

G125

—

%2, 3

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TV

= 2.5 V, and from 0.6 and 2.7 V for

L/TV

= 3.3 V.

2. Timing is guaranteed by design and characterization.

3. EC_GTX_CLK125 is used to generate the GTX clock TSECn_GTX_CLK for the eTSEC transmitter with 2% degradation.

EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated

by the TSECn_ GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and

100Base-T reference clock.

Table 7. PCIn_CLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OV

= 3.3 V ± 165 mV.

Parameter/Condition Symbol Min Typ Max Unit Notes

PCIn_CLK frequency f

PCICLK

16 — 133 MHz —

PCIn_CLK cycle time t

PCICLK

7.5 — 60 ns —

PCIn_CLK rise and fall time t

PCIKH

, t

PCIKL

0.6 1.0 2.1 ns 1, 2

PCIn_CLK duty cycle t

PCIKHKL

PCICLK

40 — 60 % 2

Notes:

1. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.

2. Timing is guaranteed by design and characterization.

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor 19

RESET Initialization

5 RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the device. The following table provides the RESET initialization AC timing specifications for the DDR

SDRAM component(s).

The following table provides the PLL lock times.

5.1 Power-On Ramp Rate

This section describes the AC electrical specifications for the power-on ramp rate requirements.

Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ESD circuitry. The

following table provides the power supply ramp rate specifications.

Table 8. RESET Initialization Timing Specifications

Parameter/Condition Min Max Unit Notes

Required assertion time of HRESET

100 — μs—

Minimum assertion time for SRESET 3 — SYSCLKs 1

PLL input setup time with stable SYSCLK before HRESET negation 100 — μs—

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

4 — SYSCLKs 1

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

2 — SYSCLKs 1

Maximum valid-to-high impedance time for actively driven POR configs with

respect to negation of HRESET

— 5 SYSCLKs 1

Note:

1. SYSCLK is the primary clock input for the device.

Table 9. PLL Lock Times

Parameter/Condition Min Max Unit

Core and platform PLL lock times — 100 μs

Local bus PLL lock time — 50 μs

PCI/PCI-X bus PLL lock time — 50 μs

Table 10. Power Supply Ramp Rate

Parameter Min Max Unit Notes

Required ramp rate for MVREF — 3500 V/s 1

Required ramp rate for VDD — 4000 V/s 1, 2

Note:

1. Maximum ramp rate from 200 to 500 mV is most critical as this range may falsely trigger the ESD circuitry.

2. VDD itself is not vulnerable to false ESD triggering; however, as per Section 22.2, “PLL Power Supply Filtering,” the

recommended AVDD_CORE, AVDD_PLAT, AVDD_LBIU, AVDD_PCI1 and AVDD_PCI2 filters are all connected to VDD.

Their ramp rates must be equal to or less than the VDD ramp rate.

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