Micron MT29F1G08ABAFA NAND Flash存储器特性与参数

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Micron NAND Flash MT29F1G08ABAFA 介绍 Micron NAND Flash MT29F1G08ABAFA 是一款高性能的 NAND Flash 存储器件，由 Micron Technology 公司生产。该芯片具有高存储密度、低功耗、高速读写速度等特点，广泛应用于各种电子产品中。 **ONFI 1.0 协议** MT29F1G08ABAFA 遵循 Open NAND Flash Interface (ONFI) 1.0 协议，是一个行业标准的 NAND Flash 接口协议。该协议定义了 NAND Flash 的存储器件的接口规范、控制协议和命令集，确保了不同厂商的 NAND Flash 存储器件之间的兼容性。 **单层单元（SLC）技术** MT29F1G08ABAFA 采用单层单元（SLC）技术，具有高存储密度、低功耗和高速读写速度等特点。SLC 技术可以确保数据的可靠性和安全性。 **存储器件组织结构** MT29F1G08ABAFA 的存储器件组织结构包括以下几个方面： * Page size：2176 字节（2048 字节 + 128 字节） * Block size：64 页（128K + 8K 字节） * Plane size：1 个 plane x 1024 块 per plane * Device size：1Gb，总共 1024 块 **异步 I/O 性能** MT29F1G08ABAFA 的异步 I/O 性能非常出色，具有以下特点： * tRC/tWC：20ns/20ns（3.3V），30ns/30ns（1.8V） **阵列性能** MT29F1G08ABAFA 的阵列性能也非常出色，具有以下特点： * 读页时间：80 μs * 编程页时间：220 μs（typ，3.3V/1.8V） * 擦除块时间：2 ms（typ） **命令集** MT29F1G08ABAFA 支持 ONFI NAND Flash 协议的命令集，包括以下几种命令： * 编程页缓存模式 * 读页缓存模式 * 永久块锁定（blocks 47:0） * 一次编程模式（OTP） * 块锁定（仅 1.8V） * 可编程驱动强度 * 读取唯一 ID * 内部数据移动 **操作状态字节** MT29F1G08ABAFA 提供了操作状态字节，软件可以通过读取该字节来检测操作的完成状态、传递/失败条件和写保护状态。 **就绪/忙信号** MT29F1G08ABAFA 还提供了就绪/忙信号（R/B#），硬件可以通过该信号来检测操作的完成状态。 **写保护信号** MT29F1G08ABAFA 的写保护信号（WP#）可以写保护整个设备。 **8 位内部 ECC** MT29F1G08ABAFA 内置 8 位内部 ECC， default enable，以确保数据的可靠性和安全性。

Architecture

These devices use NAND Flash electrical and command interfaces. Data, commands,

and addresses are multiplexed onto the same pins and received by I/O control circuits.

The commands received at the I/O control circuits are latched by a command register

and are transferred to control logic circuits for generating internal signals to control de-

vice operations. The addresses are latched by an address register and sent to a row de-

coder to select a row address, or to a column decoder to select a column address.

Data is transferred to or from the NAND Flash memory array, byte by byte (x8), through

a data register and a cache register.

The NAND Flash memory array is programmed and read using page-based operations

and is erased using block-based operations. During normal page operations, the data

and cache registers act as a single register. During cache operations, the data and cache

registers operate independently to increase data throughput. The status register reports

the status of die operations.

Figure 6: NAND Flash Die (LUN) Functional Block Diagram

Address register

Data register

Cache register

Status register

Command register

CE#

CLE

ALE

WE#

RE#

WP#

LOCK

I/Ox

Control

logic

I/O

control

R/B#

Row decode

Column decode

NAND Flash

array

(2 planes)

Note:

1. The LOCK pin is not supported on 3V devices.

Micron Confidential and Proprietary

1Gb: x8 NAND Flash Memory

Architecture

CCMTD-1725822587-10323

m78a_1gb_ecc_on_embedded_nand.pdf – Rev. E 6/19 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Asynchronous Interface Bus Operation

The bus on the device is multiplexed. Data I/O, addresses, and commands all share the

same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and

commands are always supplied on I/O[7:0].

The command sequence typically consists of a COMMAND LATCH cycle, address input

cycles, and one or more data cycles, either READ or WRITE.

Table 3: Asynchronous Interface Mode Selection

Mode

CE# CLE ALE WE# RE# I/Ox WP#

Standby

H X X X X X 0V/V

Command input L H L H X H

Address input L L H H X H

Data input L L L H X H

Data output L L L H X X

Write protect X X X X X X L

Notes:

1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = V

or V

2. WP# should be biased to CMOS LOW or HIGH for standby.

Asynchronous Enable/Standby

When the device is not performing an operation, the CE# pin is typically driven HIGH

and the device enters standby mode. The memory will enter standby if CE# goes HIGH

while data is being transferred and the device is not busy. This helps reduce power con-

sumption.

The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-

chronous memory bus as other Flash or SRAM devices. Other devices on the memory

bus can then be accessed while the NAND Flash is busy with internal operations. This

capability is important for designs that require multiple NAND Flash devices on the

same bus.

A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal

signifies that an ADDRESS INPUT cycle is occurring.

Asynchronous Commands

An asynchronous command is written from I/O[7:0] to the command register on the ris-

ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.

Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some

commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are

accepted by die (LUNs) even when they are busy.

For devices with a x16 interface, I/O[15:8] must be written with zeros when a command

is issued.

Micron Confidential and Proprietary

1Gb: x8 NAND Flash Memory

Asynchronous Interface Bus Operation

CCMTD-1725822587-10323

m78a_1gb_ecc_on_embedded_nand.pdf – Rev. E 6/19 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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