"MT8167B平板应用处理器功能规范及更新"

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本文是关于MT8167B平板电脑应用处理器功能规范的描述。这是一份严格要求2000字的文档，包含了MT8167B平板电脑应用处理器的详细功能说明。 MT8167B平板电脑应用处理器是由联发科技（MediaTek Inc.）开发的一款新一代处理器。该处理器具有一系列强大的功能和性能，是平板电脑领域的一个重要进展。该处理器的规格详细说明了其各个方面的功能和性能特点。首先，它具备强大的处理能力，搭载了高频的多核处理器，可以高效地运行各种应用程序和游戏。同时，它还支持多种内存配置和存储容量选项，以满足不同用户的需求。此外，MT8167B平板电脑应用处理器还具备出色的图形处理能力。它支持高性能GPU，可以处理复杂的图像和视频任务，并提供更好的游戏体验。此外，它还支持多屏幕显示和高分辨率输出，为用户提供更清晰、更逼真的视觉效果。在连接性方面，MT8167B平板电脑应用处理器具备丰富的接口和连接选项。它支持多种无线通信技术，如Wi-Fi和蓝牙，可以实现快速、稳定的网络连接和数据传输。同时，它还支持高速的USB接口，可以方便地连接外部设备和存储介质。此外，MT8167B平板电脑应用处理器还具备丰富的多媒体功能。它支持高清视频播放和录制，以及音频输出和处理。它还具备摄像头接口和图像处理功能，可以实现高质量的拍照和视频通话。值得一提的是，MT8167B平板电脑应用处理器还具备出色的能效特点。它采用了先进的节能技术，可以有效降低功耗并延长电池寿命。同时，它还支持智能调度和管理功能，可以根据实际使用情况自动优化性能和功耗。总之，MT8167B平板电脑应用处理器是一款功能强大、性能卓越的处理器。它具备强大的处理能力、出色的图形处理能力、丰富的连接选项和多媒体功能，以及高效的能效特点。无论是在应用程序，游戏还是多媒体任务方面，它都能满足用户的需求，并提供卓越的用户体验。相信这款处理器将为平板电脑市场带来新的发展，满足用户对性能和功能需求的日益增长。

MT8167

Tablet Applicaon Processor Funconal Specicaon

Condenal A

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Unauthorized reproducon or disclosure of this informaon in whole or in part is strictly prohibited.

Table 4-4. MT8167 Top Memory Map ...................................................................................................... 157

Table 4-5. Infrastructure System Memory Map ...................................................................................... 158

Table 4-6. Infrastructure System Memory Map ...................................................................................... 158

Table 4-7. Peripheral System Memory Map............................................................................................. 159

Table 4-8. Peripheral System Map .......................................................................................................... 160

Table 4-9. Audio System Memory Map ................................................................................................... 160

Table 4-10. MMSYS System Memory Map ............................................................................................. 160

Table 4-11 Image/VENC System Memory Map ....................................................................................... 161

Table 4-12. Video Decode System Memory Map ..................................................................................... 161

Table 4-13. On-chip Memory Controller Memory Map .......................................................................... 162

Table 4-14. DRAM Bus Signal List (refer to DRAMC side)(LPDDR3/LPDDR2) .................................. 169

Table 4-15. DRAM Bus Signal List (refer to DRAMC side)(DDR4 )(16bit DRAM) ............................... 169

Table 4-16. DRAM Bus Signal List (refer to DRAMC side)(DDR3 ) ....................................................... 170

Table 4-17. DRAM Bus Command Truth Table (LPDDR3) .................................................................... 171

Table 4-18. Relationship between Engines and Devices ......................................................................... 175

Table 4-19. BTIF Design Partition ........................................................................................................... 180

Table 4-20. BTIF Functions ..................................................................................................................... 180

Table 4-21. Test Paterns for Whole Chip Simulation .............................................................................. 181

Table 5-1. GPIO Aux Functions.................................................................................................................184

Table 5-2. GPIO Reset Status ................................................................................................................... 208

Table 5-3. GPIO Configuration Registers Summary ............................................................................... 211

Table 5-4. SPI Controller Interface .......................................................................................................... 233

Table 5-5. MSDC Functions and Address ............................................................................................... 238

Table 5-6. Sharing of Pins for MSDC. ..................................................................................................... 239

Table 5-7. AUXADC Design Partition ...................................................................................................... 250

Table 5-8. GPT Operation Mode .............................................................................................................. 259

Table 5-9. IPG Field Value ....................................................................................................................... 279

Table 5-10. LPI Sequence Transmission and Reception Functions for EEE........................................ 283

Table 5-11. TN Descriptor Format description ....................................................................................... 286

Table 5-12. FN Descriptor Format Description ...................................................................................... 287

Table 6-1. Audio Downlink Turn On Procedure ..................................................................................... 309

Table 6-2. Voice Downlink turn On Procedure ........................................................................................ 311

Table 6-3. Digital Part AFE Initialization ................................................................................................ 313

Table 6-4. Voice Uplink Turn On Procedure ........................................................................................... 313

Table 6-5. VDEC Base Address ................................................................................................................ 322

Table 6-6. Resizer Functional Specifications .......................................................................................... 330

Table 6-7. Resizer Hardware Specifications ............................................................................................ 331

Table 6-8. MDP_WROT OFST_ADDR Settings for Rotation/flip ........................................................ 348

Table 6-9. VIDO UV SEL for YUV420 Format Cooperated with CRSP ................................................ 348

Table 6-10. DISP_OVL Features ............................................................................................................. 360

Table 6-11. Sequence to Enable Module Clock ......................................................................................... 381

Table 6-12. Sequence to enable high-speed clock .................................................................................... 381

Table 6-13. Sequence of Exiting Ultra-low Power Mode on Clock Lane ................................................ 381

Table 6-14. Sequence of Sleep-in Control (entering ultra-low power mode) ......................................... 381

Table 6-15. Sequence of Sleep-out Control (exiting ultra-low power mode) ........................................ 382

Table 6-16. DPHY Timing Parameters Register Settings ....................................................................... 382

Table 6-17. DPHY Global Operation Timing Parameters Defined by MIPI spec .................................. 383

Table 6-18. Timing Compensation for HS FIFO Buffer ......................................................................... 384

Table 6-19. Config Field Description of Main Instruction ..................................................................... 385

Table 6-20. Type-0 Tx Example .............................................................................................................. 386

Table 6-21. Type-1 Tx Example ................................................................................................................ 387

Table 6-22. Type-2 Tx Example ............................................................................................................... 388

Table 6-23. Type-3 Tx Example ............................................................................................................... 389

Table 6-24. Command Mode Status in Debugging Register .................................................................. 389

Table 6-25. Example of TE Signaling Detection ..................................................................................... 395

MT8167

Tablet Applicaon Processor Funconal Specicaon

Condenal A

This document contains informaon that is proprietary to MediaTek Inc.

Unauthorized reproducon or disclosure of this informaon in whole or in part is strictly prohibited.

Table 6-26. Example of External TE Pin Detection ................................................................................ 396

Table 6-27. Example of Short Packet Transmission in Video Mode ..................................................... 396

Table 6-28. Example of Long Packet Transmission in Video Mode ...................................................... 397

Table 6-29. MIPI PLL Initial Sequence ................................................................................................... 399

Table 6-30. MIPI PLL De-initial Sequence ............................................................................................. 400

Table 6-31. Software Control Mode Example ......................................................................................... 401

Table 6-32. MIPI PLL Initial Sequence with SSC Enable ...................................................................... 401

Figure 1-1: MT8167 Block Diagram ............................................................................................................ 27

Figure 2-1: DDR3 (2*16bits) ball map view of MT8167 ........................................................................... 28

Figure 2-2: Basic timing parameter for DDR3 commands ...................................................................... 53

Figure 2-3: Basic timing parameter for DDR3 write ................................................................................. 55

Figure 2-4: Basic timing parameter for DDR3 read .................................................................................. 55

Figure 2-5: Basic timing parameter for DDR4 commands ...................................................................... 56

Figure 2-6: Basic timing parameter for DDR4 write ................................................................................. 57

Figure 2-7: Basic timing parameter for DDR4 read .................................................................................. 57

Figure 2-8: Basic timing parameter for LPDDR2 commands ................................................................. 58

Figure 2-9: Basic timing parameter for LPDDR2 write ........................................................................... 59

Figure 2-10: Basic timing parameter for LPDDR2 read ........................................................................... 59

Figure 2-11: Basic timing parameter for LPDDR3 commands ................................................................ 60

Figure 2-12: Basic timing parameter for LPDDR3 write ........................................................................... 61

Figure 2-13: Basic timing parameter for LPDDR3 read ............................................................................ 61

Figure 2-14: Power on/off sequence with XTAL ....................................................................................... 66

Figure 2-15: Power on/off sequence without XTAL ..................................................................................67

Figure 2-16: AUXADC Block Diagram ...................................................................................................... 69

Figure 2-17: PLL Block Diagram ................................................................................................................. 71

Figure 2-18: PLL Core Block Diagram........................................................................................................ 72

Figure 2-19: Audio Downlink Block Diagram ............................................................................................76

Figure 2-20: Audio Uplink Block Diagram ................................................................................................ 77

Figure 2-21:. Wi-Fi/BT spec. measurement diagram ................................................................................79

Figure 2-22: Outlines and dimensions of TFBGA 12.6mm*13.1mm, 406-ball, 0.5mm pitch package . 88

Figure 2-23: Top mark of MT8167 ............................................................................................................ 90

Figure 2-24: Power on/off sequence with XTAL ...................................................................................... 92

Figure 2-25: Power on/off sequence without XTAL ................................................................................. 93

Figure 2-26: AUXADC Block Diagram ...................................................................................................... 95

Figure 2-27: PLL Block Diagram ................................................................................................................97

Figure 2-28: PLL Core Block Diagram ...................................................................................................... 98

Figure 2-29: Audio Downlink Block Diagram ........................................................................................ 102

Figure 2-30: Audio Uplink Block Diagram ..............................................................................................103

Figure 2-31: Outlines and dimensions of TFBGA 12.6mm*13.1mm, 406-ball, 0.5mm pitch package . 113

Figure 2-32: Top mark of MT8167 ........................................................................................................... 115

Figure 3-1. Chrystal Oscillator Block Diagram ........................................................................................ 116

Figure 3-2. Clock Sources Block Diagram ................................................................................................ 119

Figure 3-3. PLL Core Block Diagram....................................................................................................... 120

Figure 3-4. PLL Power-on Sequence ........................................................................................................ 125

Figure 3-5. Clock Architecture and Hierarchy ......................................................................................... 126

Figure 3-6. Frequency Hopping Controller Block Diagram .................................................................... 129

Figure 3-7. Top Reset Generation Unit Block Diagram ..........................................................................130

Figure 3-8. MT8167 Power Domain Block Diagram ............................................................................... 131

Figure 3-9. PMIC_WRAP Overview ......................................................................................................... 135

Figure 3-10. PMIC_WRAP Architecture .................................................................................................. 136

Figure 3-11. SPI Format............................................................................................................................. 137

MT8167

Tablet Applicaon Processor Funconal Specicaon

Condenal A

This document contains informaon that is proprietary to MediaTek Inc.

Unauthorized reproducon or disclosure of this informaon in whole or in part is strictly prohibited.

Figure 3-12. SPI Parameter Configuration ............................................................................................... 137

Figure 3-13. SPI Reset Pattern .................................................................................................................. 138

Figure 3-14. SPI and WRAPPER reset flow ............................................................................................. 138

Figure 3-15. Initialization flow .................................................................................................................. 139

Figure 4-1. MT8167 Debug System Block Diagram ................................................................................. 149

Figure 4-2. System Interrupt Controller System Level Block Diagram.................................................. 150

Figure 4-3. System Interrupt Controller Block Diagram ........................................................................ 151

Figure 4-4. External Interrupt Controller Block Diagram ...................................................................... 153

Figure 4-5. DCM in Action ........................................................................................................................ 156

Figure 4-6. Top AXI Fabric and Control Blocks ...................................................................................... 157

Figure 4-7. On-Chip Memory Controller Block Diagram ........................................................................ 162

Figure 4-8. EMI/DRAM Controller Top Connection .............................................................................. 164

Figure 4-9. EMI Architecture ................................................................................................................... 165

Figure 4-10. EMI/DRAM Controller Top Connection ............................................................................. 167

Figure 4-11. EMI/DRAM Controller Top Connection ............................................................................. 173

Figure 4-12. DDRPHY Block Diagram ..................................................................................................... 173

Figure 4-13. AP_DMA Block Diagram ..................................................................................................... 176

Figure 4-14. Interface Connection between BT and Baseband System .................................................. 179

Figure 4-15.BTIF Block Diagram .............................................................................................................. 179

Figure 4-16. CQ_DMA Block Diagram ..................................................................................................... 182

Figure 5-1. GPIO Block Diagram ..............................................................................................................184

Figure 5-2. Pericfg Controller Block Diagram ......................................................................................... 217

Figure 5-3. 2x2 Keypad Matrix (4 Keys) .................................................................................................. 219

Figure 5-4. 2x2 Keypad Matrix (8 Keys) .................................................................................................. 219

Figure 5-5. 8x8 Keypad Scan Waveform ................................................................................................. 220

Figure 5-6. 5*5 Keypad Scan Waveform ................................................................................................. 220

Figure 5-7. One Key Pressed with De-bounce Mechanism Denoted ...................................................... 221

Figure 5-8. (a) Two Keys Pressed, Case 1; (b) Two Keys Pressed, Case 2 .............................................. 221

Figure 5-9. UART Block Diagram ............................................................................................................ 223

Figure 5-10. USB Controller Block Diagram ........................................................................................... 225

Figure 5-11. USBPHY RegFile Block Diagram ........................................................................................ 230

Figure 5-12. Pin Connection between SPI Master and SPI Slave .......................................................... 233

Figure-5-13. SPI Block Diagram .............................................................................................................. 233

Figure 5-14. SPI Transmission Formats .................................................................................................. 234

Figure 5-15. Operation Flow with or without PAUSE Mode .................................................................. 235

Figure 5-16. CS_N de-assert Mode .......................................................................................................... 235

Figure 5-17. MSDC block diagram ........................................................................................................... 238

Figure 5-18. MSDC Transfer Waveform .................................................................................................. 239

Figure 5-19. NFI Block Diagram .............................................................................................................. 242

Figure 5-20. Flashif Block Diagram ........................................................................................................ 243

Figure 5-21. Program Operation Sequence ............................................................................................. 244

Figure 5-22. Read Operation Sequence ................................................................................................... 245

Figure 5-23. Quad Read Mode Sequence (Address Was Sent In Single Bit Mode) .............................. 246

Figure 5-24. 4XIO Read Mode Sequence (Address Was Sent In 4bit Mode) ....................................... 247

Figure 5-25. AUXADC Block Diagram .................................................................................................... 249

Figure 5-26. SAR ADC Architecture and Conversion ............................................................................. 250

Figure 5-27. I2C Block Diagram .............................................................................................................. 254

Figure 5-28. PWM Generation Procedure .............................................................................................. 255

Figure 5-29. PWM Block Diagram ........................................................................................................... 255

Figure 5-30. sys_timer Block Diagram ................................................................................................... 256

Figure 5-31. Behavior of sys_timer Counter Timeout Value ................................................................... 257

Figure 5-32. APXGPT Block Diagram ..................................................................................................... 260

Figure 5-33. Implementation of CMOS Temperature Sensor ................................................................ 262

Figure 5-34. System Temperature Measurement Block Diagram ......................................................... 262

Figure 5-35. Programming Flow .............................................................................................................. 263

MT8167

Tablet Applicaon Processor Funconal Specicaon

Condenal A

This document contains informaon that is proprietary to MediaTek Inc.

Unauthorized reproducon or disclosure of this informaon in whole or in part is strictly prohibited.

Figure 5-36. Immediate Measurement Programming Flow .................................................................. 265

Figure 5-37. Interrupt Condition of High/Low Temperature Monitoring ............................................ 266

Figure 5-38. Finite State Machine of High/Low Temperature Monitoring .......................................... 266

Figure 5-39. Interrupt Condition of High/Low Offset Monitoring ....................................................... 267

Figure 5-40. Finite State Machine of High/Low Offset Monitoring ...................................................... 267

Figure 5-41. Pulse-width Coding ............................................................................................................. 268

Figure 5-42. Bi-phase Coding .................................................................................................................. 268

Figure 5-43. Infrared-Receiver Block Diagram ...................................................................................... 269

Figure 5-44. Ethernet MAC Top Block Diagram ..................................................................................... 271

Figure 5-45. Waveform in No Preamble Case ......................................................................................... 272

Figure 5-46. Waveform in Odd Preamble Case ...................................................................................... 272

Figure 5-47. pause_chk Block Diagram .................................................................................................. 273

Figure 5-48. pause_chk Architecture ...................................................................................................... 274

Figure 5-49. grx_main Block Diagram ..................................................................................................... 275

Figure 5-50. grx_main State Machine...................................................................................................... 275

Figure 5-51. TX Transmit Flow Chart ....................................................................................................... 277

Figure 5-52. Interframe Gap .................................................................................................................... 279

Figure 5-53. Format of Pause Frame ...................................................................................................... 280

Figure 5-54. sd_pause State Machine ...................................................................................................... 281

Figure 5-55. pause_chk State Machine ................................................................................................... 282

Figure 5-56. pause_chk Architecture ...................................................................................................... 283

Figure 5-57. Waveform of TX in LPI Mode ............................................................................................ 284

Figure 5-58. Waveform of MII Interface in LPI Mode ......................................................................... 285

Figure 5-59. Waveform in Force LPI Mode ............................................................................................ 285

Figure 5-60. Descriptor Ring Architecture ............................................................................................. 286

Figure 5-61. mtx_data Block Diagram .................................................................................................... 289

Figure 5-62. Format of IPv4 Header ....................................................................................................... 290

Figure 5-63. Format of UDP Datagram ................................................................................................... 290

Figure 5-64. format of UDP pseudo-header ............................................................................................ 291

Figure 5-65. Format of TCP Segment ....................................................................................................... 291

Figure 5-66. Format of TCP Header ......................................................................................................... 291

Figure 5-67. MAC and MMD Devices ...................................................................................................... 292

Figure 5-68. MDIO Control Module Interface ........................................................................................ 293

Figure 5-69. MDIO control module architecture .................................................................................... 294

Figure 5-70. TX-to-RX Loopback Data Path ........................................................................................... 295

Figure 5-71. RX-to-TX Loopback Data Path ........................................................................................... 295

Figure 6-1. Audio System Block Diagram.................................................................................................301

Figure 6-2. Audio System Overview ........................................................................................................ 302

Figure 6-3. TDM IN Interface Overview ................................................................................................. 302

Figure 6-4. TDM IN Interface Data Path ................................................................................................ 303

Figure 6-5. Step 1 for afe_memif_if Mechanism .................................................................................... 304

Figure 6-6. Step 2 for afe_memif_if Mechanism ................................................................................... 305

Figure 6-7. Step 3 for afe_memif_if Mechanism.................................................................................... 305

Figure 6-8. TDM IN Interface Signal ..................................................................................................... 306

Figure 6-9. Wave Form of TDM IN Interface (2 ch, 16 bck, 16 bit, I2S format) ................................... 306

Figure 6-10. Wave Form of TDM IN Interface (2 ch, 16 bck, 16 bit, EIAJ format) .............................. 306

Figure 6-11. Wave Form of TDM IN Interface (2 ch, 32 bck, 24 bit, I2S format) ................................. 307

Figure 6-12. Wave Form of TDM IN Interface (2 ch, 32 bck, 24 bit, EIAJ format) .............................. 307

Figure 6-13. Wave Form of TDM IN Interface (8 ch, 32 bck, 24 bit, I2S format) ................................ 307

Figure 6-14. Wave Form of TDM IN Interface (8 ch, 32 bck, 24 bit, EIAJ format).............................. 307

Figure 6-15. MFlexGraphics Block Diagram ............................................................................................ 315

Figure 6-16. Image Signal Processor Block Diagram .............................................................................. 317

Figure 6-17. Main Features ....................................................................................................................... 318

Figure 6-18. Video Encoder Procedure .................................................................................................... 318

Figure 6-19. Video Encoder Block Diagram ............................................................................................. 319

MT8167

Tablet Applicaon Processor Funconal Specicaon

Condenal A

This document contains informaon that is proprietary to MediaTek Inc.

Unauthorized reproducon or disclosure of this informaon in whole or in part is strictly prohibited.

Figure 6-20. Video Decoder Block Diagram ............................................................................................ 321

Figure 6-21. VDEC Hardware Architecture ............................................................................................. 321

Figure 6-22. VDEC Decoding Flow .......................................................................................................... 323

Figure 6-23. Software Reset and Power Control..................................................................................... 324

Figure 6-24. Software Reset and Power Control (turn off VDEC auto power down) ........................... 325

Figure 6-25. MDP_RDMA Block Diagram ............................................................................................. 327

Figure 6-26. MDP_RDMA State Machine .............................................................................................. 327

Figure 6-27. Software Control Flow ........................................................................................................ 329

Figure 6-28. Hardware FSM and Mutex Control Flow .......................................................................... 329

Figure 6-29. Separate 1D FIR Operations ................................................................................................ 331

Figure 6-30. 4 Tap Cubic Block Diagram ................................................................................................ 332

Figure 6-31. Cubic Accumulation (scaling ratio = 1x) ............................................................................ 333

Figure 6-32. Cubic Accumulation (scaling ratio = 1/2x) ........................................................................ 334

Figure 6-33. Suggested Algorithm v.s. Supported Size .......................................................................... 335

Figure 6-34. Programming Guide............................................................................................................ 336

Figure 6-35. Display 2D Sharpness Block Diagram ............................................................................... 338

Figure 6-36. Sharpness Core Block Diagram .......................................................................................... 338

Figure 6-37. Visual Effect of 2-dimensional Sharpness ......................................................................... 339

Figure 6-38. Visual Effect of Peaking by Color ....................................................................................... 339

Figure 6-39. MDP_TDSHP State Machine ............................................................................................ 340

Figure 6-40. Usage Scenarios .................................................................................................................. 340

Figure 6-41 Gain Curve Control of Charpness ......................................................................................... 341

Figure 6-42. Demo Curve Control of Luma Adjustment ......................................................................... 341

Figure 6-43. MDP_WDMA of Display System ....................................................................................... 342

Figure 6-44. MDP_WDMA Block Diagram ............................................................................................ 343

Figure 6-45 WDMA State Machine ......................................................................................................... 343

Figure 6-46. MDP_WROT Block Diagram ............................................................................................. 345

Figure 6-47. MDP_WROT State Machine .............................................................................................. 346

Figure 6-48. Firmware Settings of OFST_ADDR in 0° rotation (scan-line) ........................................ 347

Figure 6-49. Firmware Settings of OFST_ADDR in 90° rotation (scan-line) ..................................... 347

Figure 6-50. Firmware Settings of OFST_ADDR in 180° rotation (scan-line) .................................... 347

Figure 6-51. Firmware settings of OFST_ADDR in 270° rotation (scan-line) ...................................... 348

Figure 6-52. Probability of Crossing 256-byte Boundary by Random Access ....................................... 351

Figure 6-53. Scan-line Request without Considering 256-byte Boundary ............................................. 351

Figure 6-54. Scan-line Request Considering 256-byte Boundary ......................................................... 352

Figure 6-55 Burst in 270° Rotation with/without flip ............................................................................ 352

Figure 6-56. Display System DISP_RDMA............................................................................................. 353

Figure 6-57. DISP_RDMA Block Diagram .............................................................................................. 354

Figure 6-58. General Programming Sequence ........................................................................................ 355

Figure 6-59. Basic Memory Mode Configuration ................................................................................... 355

Figure 6-60. Programmable Color Matrix .............................................................................................. 355

Figure 6-61. Byte/RGB Swap ................................................................................................................... 356

Figure 6-62. Display System DISP_WDMA ............................................................................................ 357

Figure 6-63. DISP_WDMA Block Diagram ............................................................................................ 358

Figure 6-64. WDMA State Machine ........................................................................................................ 358

Figure 6-65. DISP_OVL Block Diagram .................................................................................................. 361

Figure 6-66. Typical DISP_OVL Programming Procedure.................................................................... 362

Figure 6-67. Color Processor.................................................................................................................... 364

Figure 6-68. 20 Hue Phases Distribution ............................................................................................... 364

Figure 6-69. Partial Hue Adjustment Example ...................................................................................... 365

Figure 6-70. Contrast/Brightness Adjustment Example ....................................................................... 365

Figure 6-71. Chroma Boost Demonstration ............................................................................................ 366

Figure 6-72. Example of Partial S Adjustment for One Hue Phase ....................................................... 366

Figure 6-73. Illustration of Global Saturation Adjustment .................................................................... 367

Figure 6-74. Color Correction Block Diagram ........................................................................................ 368

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