S3C2440A 32-BIT微控制器用户手册（修订1）

CPU_S3C2440

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xvi S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 17 Real Time Clock

Overview .............................................................................................................................................17-1

Features .....................................................................................................................................17-1

Real Time Clock Operation...........................................................................................................17-2

Leap Year Generator....................................................................................................................17-2

Read/Write Registers...................................................................................................................17-2

Backup Battery Operation ............................................................................................................17-2

Alarm Function............................................................................................................................17-3

TICK Time Interrupt ......................................................................................................................17-3

32.768kHz X-Tal Connection Example ..........................................................................................17-3

Real Time Clock Special Registers .......................................................................................................17-4

Real Time Clock Control (RTCCON) Register .................................................................................17-4

TICK Time Count (TICNT) Register ................................................................................................17-4

RTC Alarm Control (RTCALM) Register..........................................................................................17-5

ALARM Second Data (ALMSEC) Register .....................................................................................17-6

ALARM Min Data (ALMMIN) Register............................................................................................17-6

ALARM Hour Data (ALMHOUR) Register.......................................................................................17-6

ALARM Date Data (ALMDATE) Register........................................................................................17-7

ALARM Mon Data (ALMMON) Register .........................................................................................17-7

ALARM Year Data (ALMYEAR) Register .......................................................................................17-7

BCD Second (BCDSEC) Register .................................................................................................17-8

BCD Minute (BCDMIN) Register....................................................................................................17-8

BCD Hour (BCDHOUR) Register ...................................................................................................17-8

BCD Date (BCDDATE) Register....................................................................................................17-9

BCD Day (BCDDAY) Register.......................................................................................................17-9

BCD Month (BCDMON) Register...................................................................................................17-9

BCD Year (BCDYEAR) Register ...................................................................................................17-10

Chapter 18 Watchdog Timer

Overview .............................................................................................................................................18-1

Features .....................................................................................................................................18-1

Watchdog Timer Operation...........................................................................................................18-2

Wtdat & Wtcnt ............................................................................................................................18-2

Consideration of Debugging Environment .......................................................................................18-2

Watchdog Timer Special Registers .......................................................................................................18-3

Watchdog Timer Control (WTCON) Register...................................................................................18-3

Watchdog Timer Data (WTDAT) Register.......................................................................................18-4

Watchdog Timer Count (WTCNT) Register .....................................................................................18-4

S3C2440A MICROCONTROLLER xvii

Table of Contents (Continued)

Chapter 19 MMC/SD/SDIO Controller

Features .............................................................................................................................................19-1

Block Diagram ....................................................................................................................................19-1

SD Operation ......................................................................................................................................19-2

SDIO Operation...................................................................................................................................19-3

SDI Special Registers ..........................................................................................................................19-4

SDI Control Register (SDICON).....................................................................................................19-4

SDI Baud Rate Prescaler Register (SDIPRE) .................................................................................19-4

SDI Command Argument Register (SDICmdArg).............................................................................19-5

SDI Command Control Register (SDICmdCon)................................................................................19-5

SDI Command Status Register (SDICmdSta) .................................................................................19-6

SDI Response Register 0 (SDIRSP0) ............................................................................................19-6

SDI Response Register 1 (SDIRSP1) ............................................................................................19-6

SDI Response Register 2 (SDIRSP2) ............................................................................................19-7

SDI Response Register 3 (SDIRSP3) ............................................................................................19-7

SDI Data / Busy Timer Register (SDIDTimer)..................................................................................19-7

SDI Block Size Register (SDIBSize)..............................................................................................19-7

SDI Data Control Register (SDIDatCon) .........................................................................................19-8

SDI Data Remain Counter Register (ADIDatCnt).............................................................................19-9

SDI Data Status Register (ADIDatSta)...........................................................................................19-9

SDI FIFO Status Register (SDIFSTA)............................................................................................19-10

SDI Interrupt Mask Register (SDIIntMsk)........................................................................................19-11

SDI Data Register (SDIDAT) .........................................................................................................19-12

Chapter 20 IIC-Bus Interface

Overview .............................................................................................................................................20-1

IIC-Bus Interface..........................................................................................................................20-3

Start and Stop Conditions ............................................................................................................20-3

Data Transfer Format ...................................................................................................................20-4

ACK Signal Transmission.............................................................................................................20-5

Read-Write Operation ..................................................................................................................20-6

Bus Arbitration Procedures...........................................................................................................20-6

Abort Conditions..........................................................................................................................20-6

Configuring IIC-Bus ......................................................................................................................20-6

Flowcharts of Operations in Each Mode.........................................................................................20-7

IIC-Bus Interface Special Registers .......................................................................................................20-11

Multi-Master IIC-Bus Control (IICCON) Register ..............................................................................20-11

Multi-Master IIC-Bus Control/Status (IICSTAT) Register...................................................................20-12

Multi-Master IIC-Bus Address (IICADD) Register.............................................................................20-13

Multi-Master IIC-Bus Transmit/Receive Data Shift (IICDS) Register...................................................20-13

Multi-Master IIC-Bus Line Contro l(IICLC) Register ..........................................................................20-14

xviii S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 21 IIS-Bus Interface

Overview .............................................................................................................................................21-1

Block Diagram ....................................................................................................................................21-2

Functional Descriptions........................................................................................................................21-2

Transmit or Receive Only Mode ....................................................................................................21-2

Dma Transfer ..............................................................................................................................21-3

Transmit and Receive Mode..........................................................................................................21-3

Audio Serial Interface Format................................................................................................................21-3

IIS-Bus Format ............................................................................................................................21-3

MSB (Left) Justified .....................................................................................................................21-3

Sampling Frequency and Master Clock .........................................................................................21-4

IIS-Bus Interface Special Registers .......................................................................................................21-5

IIS Control (IISCON) Register........................................................................................................21-5

IIS Mode Register (IISMOD) Register.............................................................................................21-6

IIS Prescaler (IISPSR) Register.....................................................................................................21-7

IIS FIFO Control (IISFCON) Register..............................................................................................21-8

IIS FIFO (IISFIFO) Register...........................................................................................................21-8

Chapter 22 SPI

Overview .............................................................................................................................................22-1

Features .....................................................................................................................................22-1

Block Diagram ............................................................................................................................22-2

SPI Operation .....................................................................................................................................22-3

Programming Procedure...............................................................................................................22-3

SPI Transfer Format.....................................................................................................................22-4

Transmitting Procedure for DMA ...................................................................................................22-5

Receiving Procedure for DMA .......................................................................................................22-5

SPI Special Registers ..........................................................................................................................22-6

SPI Control Register ....................................................................................................................22-6

SPI Status Register.....................................................................................................................22-7

SPI Pin Control Register ..............................................................................................................22-8

SPI Baud Rate Prescaler Register ................................................................................................22-9

SPI Tx Data Register ...................................................................................................................22-9

SPI Rx Data Register...................................................................................................................22-9

S3C2440A MICROCONTROLLER xix

Table of Contents (Continued)

Chapter 23 Camera Interface

Overview .............................................................................................................................................23-1

Features .....................................................................................................................................23-1

Block Diagram ............................................................................................................................23-2

Timing Diagram ...........................................................................................................................23-3

Camera Interface Operation ..................................................................................................................23-5

Two DMA Paths ..........................................................................................................................23-5

Clock Domain .............................................................................................................................23-5

Frame Memory Hirerarchy ............................................................................................................23-6

Memory Storing Method...............................................................................................................23-8

Timing Diagram for Register Setting ..............................................................................................23-9

Timing Diagram for Last IRQ.........................................................................................................23-10

Camera Interface Special Registers.......................................................................................................23-11

Source Format Register ...............................................................................................................23-11

Window Option Register...............................................................................................................23-12

Global Control Register ................................................................................................................23-13

Y1 Start Address Register............................................................................................................23-13

Y2 Start Address Register............................................................................................................23-13

Y3 Start Address Register............................................................................................................23-14

Y4 Start Address Register............................................................................................................23-14

CB1 Start Address Register .........................................................................................................23-14

CB2 Start Address Register .........................................................................................................23-14

CB3 Start Address Register .........................................................................................................23-15

CB4 Start Address Register .........................................................................................................23-15

CR1 Start Address Register .........................................................................................................23-15

CR2 Start Address Register .........................................................................................................23-15

CR3 Start Address Register .........................................................................................................23-16

CR4 Start Address Register .........................................................................................................23-16

Codec Target Format Register ......................................................................................................23-17

Codec Dma Control Register ........................................................................................................23-19

Register Setting Guide for Codec Scaler and Preview Scaler ...........................................................23-20

Codec Pre-Scaler Control Register 1.............................................................................................23-21

Codec Pre-Scaler Control Register 2.............................................................................................23-21

Codec Main-Scaler Control Register..............................................................................................23-22

Codec Dma Target Area Register..................................................................................................23-22

Codec Status Register.................................................................................................................23-23

RGB1 Start Address Register.......................................................................................................23-23

RGB2 Start Address Register.......................................................................................................23-23

RGB3 Start Address Register.......................................................................................................23-24

RGB4 Start Address Register.......................................................................................................23-24

Preview Target Format Register ....................................................................................................23-24

Preview DMA Control Register ......................................................................................................23-25

xx S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 23 Camera Interface (Continued)

Preview Pre-Scaler Control Register 1 ...........................................................................................23-25

Preview Pre-Scaler Control Register 2 ...........................................................................................23-26

Preview Main-Scaler Control Register ............................................................................................23-26

Preview DMA Target Area Register................................................................................................23-26

Preview Status Register ...............................................................................................................23-27

Image Capture Enable Register.....................................................................................................23-27

Chapter 24 AC97 Controller

Overview .............................................................................................................................................24-1

Features .....................................................................................................................................24-1

AC97 Controller Operation....................................................................................................................24-2

Block Diagram ............................................................................................................................24-2

Internal Data Path........................................................................................................................24-3

Operation Flow Chart ...........................................................................................................................24-4

AC-Link Digital Interface Protocol..........................................................................................................24-5

AC-Link Output Frame (SDATA_OUT) ...........................................................................................24-6

AC-Link Input Frame (SDATA_IN) .................................................................................................24-6

AC97 Powerdown ................................................................................................................................24-7

AC97 Controller Special Registers ........................................................................................................24-9

AC97 Global Control Register (AC_GLBCTRL) ...............................................................................24-9

AC97 Global Status Register (AC_GLBSTAT) ................................................................................24-10

AC97 Codec Command Register (AC_CODEC_CMD).....................................................................24-10

AC97 Codec Status Register (AC_CODEC_STAT) .........................................................................24-11

AC97 PCM Out/In Channel FIFO Address Register (AC_PCMADDR) ...............................................24-11

AC97 MIC in Channel FIFO Address Register (AC_MICADDR) ........................................................24-12

AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA).....................................................24-12

AC97 MIC in Channel FIFO Data Register (AC_MICDATA)..............................................................24-12

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