RISC-V调试规范V1.0稳定版：兼容与改进

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2 RISC-V Debug Speciﬁcation Version 1.0-STABLE

DMI

Debug Module Interface (see Section 3.1).

DR JTAG Data Register.

DTM

Debug Transport Module (see Section 6).

DXLEN

Debug XLEN, which is the widest XLEN a hart supports, ignoring the current value of MXL

in misa.

essential feature

An essential feature must be present in order for debug to work correctly.

GPR

General Purpose Register.

hardware platform

A single system consisting of one or more components.

hart

A hardware thread in a RISC-V core.

IDCODE

32-bit Identiﬁcation CODE, and a JTAG instruction that returns the IDCODE value.

IR JTAG Instruction Register.

JTAG

Refers to work done by IEEE’s Joint Test Action Group, described in IEEE 1149.1.

legacy feature

A legacy feature should only be implemented to support legacy hardware that is present in a

system.

Minimal RISC-V Debug Speciﬁcation

A subset of the full Debug Speciﬁcation that allows for very small implementations. See

Chapter 3.

NAPOT

Naturally Aligned Power-Of-Two.

NMI

Non-Maskable Interrupt.

physical address

An address that is directly usable on the system bus.

recommended feature

A recommended feature is not required for debug to work correctly, but it is so useful that it

should not be omitted without good reason.

4 RISC-V Debug Speciﬁcation Version 1.0-STABLE

Version 1.0 is almost entirely forwards and backwards compatible with Version 0.13.

1.2.1.1 Bugﬁxes from 0.13 to 1.0

Changes that ﬁx a bug in the spec:

1. Fix order of operations described in sbdata0. #392

2. Resume ack is set after resume, in Section 3.5. #400

3. sselect applies to svalue. #402

4. mte only applies when action=0. #411

5. aamsize does not aﬀect Argument Width. #420

6. Clarify that harts halt out of reset if haltreq =1. #419

1.2.1.2 Incompatible Changes from 0.13 to 1.0

Changes that are not backwards-compatible. Debuggers or hardware implementations that imple-

ment 0.13 will have to change something in order to implement 1.0:

1. Make haltsum0 optional if there is only one hart. #505

2. System bus autoincrement only happens if an access actually takes place. (sbdata0) #507

3. Bump version to 3. #512

4. Require debugger to poll dmactive after lowering it. #566

5. Add pending to icount. #574

6. When a selected trigger is disabled, tdata2 and tdata3 can be written with any value sup-

ported by any of the types this trigger supports. #721

7. tcontrol ﬁelds only apply to breakpoint traps, not any trap. #723

8. If version is greater than 0, then hit0 (previously called mcontrol6.hit) now contains 0 when a

trigger ﬁres more than one instruction after the instruction that matched. (This information

is now reﬂected in hit1.) #795

9. If version is greater than 0, then bit 20 of mcontrol6 is no longer used for timing information.

(Previously the bit was called mcontrol6.timing.) #807

10. If version is greater than 0, then the encodings of size for sizes greater than 64 bit have

changed. #807

1.2.1.3 Minor Changes from 0.13 to 1.0

Changes that slightly modify deﬁned behavior. Technically backwards incompatible, but unlikely

to be noticeable:

1. stopcount only applies to hart-local counters. #405

2. version may be invalid when dmactive =0. #414

3. Address triggers (mcontrol) may ﬁre on any accessed address. #421

4. All trigger registers (Section 5.3) are optional. #431

RISC-V Debug Speciﬁcation Version 1.0-STABLE 5

5. When extending IR, bypass still is all ones. #437

6. ebreaks and ebreaku are WARL. #458

7. NMIs are disabled by stepie. #465

8. R/W1C ﬁelds should be cleared by writing every bit high. #472

9. Specify trigger priorities in Table 5.2 relative to exceptions. #478

10. Time may pass before dmactive becomes high. #500

11. Clear MPRV when resuming into lower privilege mode. #503

12. Halt state may not be preserved across reset. #504

13. Hardware should clear trigger action when dmode is cleared and action is 1. #501

14. Change quick access exceptions to halt the target in Section 3.7.1.2. #585

15. Writing 0 to tdata1 forces a state where tdata2 and tdata3 are writable. #598

16. Solutions to deal with reentrancy in Section 5.4 prevent triggers from matching, not merely

ﬁring. This primarily aﬀects icount behavior. #722

17. Attempts to access an unimplemented CSR raise an illegal instruction exception. #791

1.2.1.4 New Features from 0.13 to 1.0

New backwards-compatible feature that did not exist before:

1. Add halt groups and external triggers in Section 3.6. #404

2. Reserve some DMI space for non-standard use. See custom, and custom0 through custom15.

#406

3. Reserve trigger type values for non-standard use. #417

4. Add nmi bit to itrigger. #408 and #709

5. Recommend matching on every accessed address. #449

6. Add resume groups in Section 3.6. #506

7. Add relaxedpriv. #536

8. Move scontext, renaming original to mscontext, and create hcontext. #535

9. Add mcontrol6, deprecating mcontrol. #538

10. Add hypervisor support: ebreakvs, ebreakvu, v, hcontext, mcontrol, mcontrol6, and priv.

#549

11. Optionally make anyunavail and allunavail sticky, controlled by stickyunavail. #520

12. Add tmexttrigger to support trigger module external trigger inputs. #543

13. Describe mcontrol and mcontrol6 behavior with atomic instructions. #561

14. Trigger hit bits must be set on ﬁre, may be set on match. #593

15. Add sbytemask and sbytemask to textra32 and textra64. #588

16. Allow debugger to request harts stay alive with keepalive bit in Section 3.14.2. #592

17. Add ndmresetpending to allow a debugger to determine when ndmreset is complete. #594

18. Add intctl to support triggers from an interrupt controller. #599

1.2.1.5 Incompatible Changes During 1.0 Stable

Backwards-incompatible changes between two versions that are both called 1.0 stable.

6 RISC-V Debug Speciﬁcation Version 1.0-STABLE

1. nmi was moved from etrigger to itrigger, and is now subject to the mode bits in that

trigger.

2. #728 introduced Message Registers, which were later removed in #878.

3. It may not be possible to read the contents of the Program Buﬀer using the progbuf registers.

#731

4. tcontrol ﬁelds apply to all traps, not just breakpoint traps. This reverts #723. #880

1.3 About This Document

1.3.1 Structure

This document contains two parts. The main part of the document is the speciﬁcation, which is

given in the numbered chapters. The second part of the document is a set of appendices. The

information in the appendices is intended to clarify and provide examples, but is not part of the

actual speciﬁcation.

1.3.2 ISA vs. non-ISA

This speciﬁcation contains both ISA and non-ISA parts. The ISA parts deﬁne self-contained ISA

extensions. The other parts of the document describe the non-ISA external debug extension.

Chapters whose contents are solely one or the other are labeled as such in their title. Chapters

without such a label apply to both ISA and non-ISA.

1.3.3 Register Deﬁnition Format

All register deﬁnitions in this document follow the format shown below. A simple graphic shows

which ﬁelds are in the register. The upper and lower bit indices are shown to the top left and top

right of each ﬁeld. The total number of bits in the ﬁeld are shown below it.

After the graphic follows a table which for each ﬁeld lists its name, description, allowed accesses,

and reset value. The allowed accesses are listed in Table 1.2. The reset value is either a constant

or “Preset.” The latter means it is an implementation-speciﬁc legal value.

Parts of the register which are currently unused are labeled with the number 0. Software must only

write 0 to those ﬁelds, and ignore their value while reading. Hardware must return 0 when those

ﬁelds are read, and ignore the value written to them.

This behavior enables us to use those ﬁelds later without having to increase the values in the

version ﬁelds.

Names of registers and their ﬁelds are hyperlinks to their deﬁnition, and are also listed in the index

on page 117.

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