MIPS Open 64架构手册II-A：MIPS64指令集详览

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MIPS Open 64 指令集手册卷二是一份详细的专业文档，由MIPS Tech, LLC发布，旨在为程序设计者提供对MIPS64指令集的深入理解。该手册是MIPS Architecture for Programmers系列的一部分，专为第II-A卷，主要关注MIPS64架构，这是一种扩展的32位MIPS指令集，特别适用于64位计算环境。文档MD00087在第六版修订6.07，更新日期为2019年3月15日。它包含了MIPS64指令集的完整参考手册，这些指令集对于支持高性能计算、系统软件开发以及嵌入式系统等领域至关重要。手册涵盖了各种指令的详细介绍，包括数据类型处理、算术运算、逻辑操作、控制转移、内存访问等，这些都是现代处理器设计中的核心元素。作为MIPS Open许可的一部分，此文档受版权保护，并且受专利、商标、不公平竞争法等法律约束，仅限于在MIPS许可框架下使用。这意味着用户在复制、修改或传播文档内容时必须得到MIPS公司的明确书面许可。MIPS公司在指令集技术方面拥有广泛的知识产权，包括在美国和其他国家的已授权和待申请专利。该手册不仅提供了技术细节，还可能包含第三方开发的材料，这些内容可能是为了补充和完善MIPS64指令集的功能和应用示例。阅读这份手册可以帮助开发者优化代码性能，理解64位架构的优势，以及如何充分利用MIPS指令集来实现高效的程序设计。 MIPS Open 64 指令集手册卷二是硬件开发者和软件工程师的宝贵参考资料，它提供了关于如何在64位平台上编写、调试和优化代码的全面指南。通过深入研究其中的内容，程序员可以更好地利用MIPS64技术构建强大而兼容的系统。

MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set Reference Manual — Revision 6.07

0 Legacy “0” behaves like R0 - read as zero, nonzero writes ignored.

Legacy “0” should not be defined for any new control register fields; R0 should be used instead.

HW returns 0 when read.

HW ignores writes.

Only zero should be written, or, value read from reg-

ister.

R/W0 Like R/W, except that writes of non-zero to a R/W0 field are ignored.

E.g. Status.NMI

Hardware may set or clear an R/W0 bit.

Hardware ignores software writes of nonzero to an

R/W0 field. Neither the occurrence of such writes,

nor the values written, affects hardware behavior.

Software writes of 0 to an R/W0 field may have an

effect.

Hardware may return 0 or nonzero to software

reads of an R/W0 bit.

If software performs an mtc0 instruction which

writes a non-zero value to an R/W0 field, the write

to the R/W0 field will be ignored, but permitted

writes to other fields in the register will not be

affected.

Software can only clear an R/W0 bit.

Software writes 0 to an R/W0 field to clear the field.

Software writes nonzero to an R/W0 bit in order to

guarantee that the bit is not affected by the write.

Table 1.2 Read/Write Register Field Notation (Continued)

Read/Write

Notation Hardware Interpretation Software Interpretation

MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set Reference Manual — Revision 6.07

2.1.1 Instruction Fields

Fields encoding the instruction word are shown in register form at the top of the instruction description. The follow-

ing rules are followed:

• The values of constant fields and the opcode names are listed in uppercase (SPECIAL and ADD in Figure 2.2).

Constant values in a field are shown in binary below the symbolic or hexadecimal value.

• All variable fields are listed with the lowercase names used in the instruction description (rs, rt, and rd in Figure

2.2).

• Fields that contain zeros but are not named are unused fields that are required to be zero (bits 10:6 in Figure 2.2).

If such fields are set to non-zero values, the operation of the processor is UNPREDICTABLE.

Figure 2.2 Example of Instruction Fields

2.1.2 Instruction Descriptive Name and Mnemonic

The instruction descriptive name and mnemonic are printed as page headings for each instruction, as shown in Figure

2.3.

Figure 2.3 Example of Instruction Descriptive Name and Mnemonic

2.1.3 Format Field

The assembler formats for the instruction and the architecture level at which the instruction was originally defined are

given in the Format field. If the instruction definition was later extended, the architecture levels at which it was

extended and the assembler formats for the extended definition are shown in their order of extension (for an example,

see C.cond.fmt). The MIPS architecture levels are inclusive; higher architecture levels include all instructions in pre-

vious levels. Extensions to instructions are backwards compatible. The original assembler formats are valid for the

extended architecture.

Figure 2.4 Example of Instruction Format

The assembler format is shown with literal parts of the assembler instruction printed in uppercase characters. The

variable parts, the operands, are shown as the lowercase names of the appropriate fields.

The architectural level at which the instruction was first defined, for example “MIPS32” is shown at the right side of

the page. Instructions introduced at different times by different ISA family members, are indicated by markings such

as “MIPS64, MIPS32 Release 2”. Instructions removed by particular architecture release are indicated in the Avail-

ability section.

31 26 25 21 20 16 15 11 10 6 5 0

SPECIAL

000000

00000

ADD

100000

6 5555 6

rs rt rd

Add Word ADD

Format: ADD fd,rs,rt MIPS32

MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set Reference Manual — Revision 6.07

There can be more than one assembler format for each architecture level. Floating point operations on formatted data

show an assembly format with the actual assembler mnemonic for each valid value of the fmt field. For example, the

ADD.fmt instruction lists both ADD.S and ADD.D.

The assembler format lines sometimes include parenthetical comments to help explain variations in the formats (once

again, see C.cond.fmt). These comments are not a part of the assembler format.

2.1.4 Purpose Field

The Purpose field gives a short description of the use of the instruction.

Figure 2.5 Example of Instruction Purpose

2.1.5 Description Field

If a one-line symbolic description of the instruction is feasible, it appears immediately to the right of the Description

heading. The main purpose is to show how fields in the instruction are used in the arithmetic or logical operation.

Figure 2.6 Example of Instruction Description

The body of the section is a description of the operation of the instruction in text, tables, and figures. This description

complements the high-level language description in the Operation section.

This section uses acronyms for register descriptions. “GPR rt” is CPU general-purpose register specified by the

instruction field rt. “FPR fs” is the floating point operand register specified by the instruction field fs. “CP1 register

fd” is the coprocessor 1 general register specified by the instruction field fd. “FCSR” is the floating point Control /

Status register.

2.1.6 Restrictions Field

The Restrictions field documents any possible restrictions that may affect the instruction. Most restrictions fall into

one of the following six categories:

•V

alid values for instruction fields (for example, see floating point ADD.fmt)

• ALIGNMENT requirements for memory addresses (for example, see LW)

• Valid values of operands (for example, see ALNV.PS)

• Valid operand formats (for example, see floating point ADD.fmt)

Purpose: Add Word

To add 32-bit integers. If an overflow occurs, then trap.

Description: GPR[rd] ← GPR[rs] + GPR[rt]

The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit

result.

• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination

• If the addition does not overflow, the 32-bit result is signed-extended and placed into

GPR rd.

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