Xilinx ISE Simulator深度教程：设计与硬件设备开发指南

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ISE仿真器是Xilinx公司提供的一款专门用于FPGA（Field-Programmable Gate Array）设计和验证的重要工具，它在Xilinx ISE集成开发环境（Integrated Software Environment, ISE）中占据核心地位。这款工具集成了设计、编程、配置和调试功能，是硬件描述语言（Hardware Description Language, HDL）如Verilog和VHDL设计流程中的关键环节。 UG682（版本1.0，发布日期：2009年4月27日）是一份深入教程，详细介绍了ISE Simulator（ISim），它是ISE软件套件中的模拟器部分。ISim允许用户对设计进行实时仿真，以便在实际硬件部署之前检查和优化设计的性能、功能和时序行为。通过这款模拟器，设计人员能够模拟信号的行为，观察电路的波形，测试系统级功能，并识别潜在的问题，如逻辑错误、同步问题或时钟周期冲突。该文档强调了使用ISE Simulator的特定权限规定，用户必须获得Xilinx的书面许可才能复制、分发或以任何形式（包括电子、机械、复印、录音等）使用文档。Xilinx明确表示不对文档中的任何错误或遗漏承担责任，并保留随时更新文档的权利。此外，Xilinx提供的技术支持和协助并不构成对文档内容的保证。在使用ISE仿真器时，设计师需要注意以下几点： 1. **文档依赖性**：理解并遵循文档中的指导，因为任何改动可能会影响设计的正确实现。 2. **版权和许可**：确保所有使用的代码和IP遵守相应的许可证协议，避免知识产权纠纷。 3. **错误处理与更新**：尽管Xilinx不承诺纠正文档错误，但及时关注官方发布的任何修正或更新信息，以保持设计的最新状态。 4. **仿真策略**：学会有效地使用ISim进行波形分析，确定设计的稳定性和性能指标，这对于调试和优化至关重要。 ISE仿真器是Xilinx ISE工具包中的核心组成部分，对于从事FPGA设计的专业人士来说，熟练掌握其使用方法和理解文档中的注意事项，是确保设计质量和效率的关键。随着技术的发展，ISE和相关教程会不断更新，因此持续学习和适应新版本的功能也十分必要。

ISE Simulator (ISim) In-Depth Tutorial www.xilinx.com 3

UG682 (v1.0) April 27, 2009

Chapter 2

Using ISE Simulator from ISE Project

Navigator

Overview of ISim ISE Integrated Flow

The Xilinx

ISE software provides an integrated flow with the Xilinx ISE Simulator (ISim)

that allows simulations to be launched directly from the Xilinx Project Navigator (ISE). All

simulation commands that prepare the ISim simulation are generated by ISE Project

Navigator and automatically run in the background when simulating a design using this

flow.

Getting Started

Software Requirements

To use this tutorial, you must install the following software:

1. ISE WebPACK™ 11, or

2. One of the ISE Design Suite 11 Editions (Logic, DSP, Embedded, System)

For more information about installing Xilinx

software, see the ISE Release Notes and Installation

Guide at: http://www.xilinx.com/support/software_manuals.htm

Installing the Tutorial Design Files

Design files for this tutorial can be downloaded from:

http://www.xilinx.com/support/techsup/tutorials/tutorials11.htm

After you have downloaded the tutorial project files from the Web, unzip them into an

easily accessible directory with full read and write permissions.

The contents of the tutorial project files are as follows:

• sources: Folder containing all the HDL files necessary for a functional simulation of

the design.

• scripts: Folder containing incomplete script files to run the simulation. These script

files will be completed as you go through the tutorial.

• completed: Folder containing completed script, simulation and wave configuration

files, as well as a completed ISE 11 project of the tutorial design, for comparison

purposes.

4 www.xilinx.com ISE Simulator (ISim) In-Depth Tutorial

UG682 (v1.0) April 27, 2009

Design Description

The ISim In-Depth Tutorial provides a design which the reader can use to become familiar

performing some basic simulation steps while using the ISim software.

The tutorial design is a simple demonstration of the Dynamic Reconfiguration feature of

the Virtex

-5 Digital Clock Manager (DCM).

Using the Virtex-5 DCM, the design generates an output clock using the following

relationship:

Output Clock = Input Clock * (Multiplier / Divider)

Using the Dynamic Reconfiguration Ports (DRP) in the DCM, the design allows the user to

re-define the Multiplier and Divider parameters to generate different output frequencies.

Functional Blocks

The tutorial design consists of the following functional blocks.

• drp_dcm (drp_dcm.vhd)

Virtex-5 DCM macro with internal feedback, frequency controlled output, duty-cycle

correction, and Dynamic Reconfiguration ability.

The CLKFX_OUT output provides a clock that is defined by the following

relationship:

CLKFX_OUT = CLKIN_IN * (Multiplier/Divider)

For example, using a 100 MHz input clock, setting the Multiplier factor to 6, and

Divider factor to 5, produces a 120 MHz CLKFX_OUT output clock.

Using the DRP ports of the DCM, the Multiplier (M) and Divider (D) parameters can

be dynamically redefined to produce different CLKFX_OUT frequencies. For the

purposes of this tutorial, it suffices to show how the Multiply and Divide parameters

are provided to the DCM via the 16-bit wide DI_IN port:

DI_IN[15:8] = M – 1

DI_IN[7:0] = D – 1

For example, for an M/D factor of 6 / 5, DI_IN = 0504h.

• drp_stmach (drp_stmach.vhd)

This module describes a Dynamic Reconfiguration Controller. The DRP controller

asserts and monitors the DCM DRP signals in order to perform a dynamic

reconfiguration cycle.

A dynamic reconfiguration cycle is started by asserting the drp_start signal. Following

this step, the DRP Controller asserts the appropriate DCM DRP pins in order to

complete a full Dynamic Reconfiguration cycle.

Signal drp_done indicates a successful completion of a dynamic reconfiguration cycle.

• drp_demo (drp_demo.vhd)

This is the top module of the tutorial design which connects the DCM macro and the

DRP controller modules to the external I/O ports.

• drp_demo_tb (drp_demo_tb.vhd)

Self-checking HDL test bench. Refer to Design Self-Checking Test Bench for more

information.

ISE Simulator (ISim) In-Depth Tutorial www.xilinx.com 5

UG682 (v1.0) April 27, 2009

Simulating the Design

Design Self-Checking Test Bench

To test the functionality of this design, a self-checking test bench has been provided. (Refer to

source file drp_demo_tb.vhd in the sources folder.) A self-checking test bench contains a validation

routine or function that compares sampled values from the simulation against expected results. The

self-checking test bench provided for this design performs the following functions.

• Generates a 100 MHz input clock for the design system clock (clk_in).

• Performs four different tests in order to dynamically change the output frequency of

the design. In each test, a DRP cycle is started (using the drp_start signal) to set the

output clock to a different frequency. The following table shows the desired output

frequency and Multiplier/Divider parameters used for each test.

• In each test, the test bench will compare the expected clock period and the clock period

measured during simulation. Based on the comparison results, messages to the simulator will

be written indicating success or failure.

• Upon completion of the simulation, a summary report is provided, listing which tests

passed or failed.

Note:

For more details on the functionality of this design, refer to the in-line comments included in

the sources of the design.

Simulating the Design

Thanks to an intuitive integrated flow, you can easily and quickly perform behavioral and

timing simulations of your design in the ISE Project Navigator software. Using the

integrated flow, you can quickly set up simulation properties and launch the ISim software

with a few clicks of the mouse.

We shall demonstrate how ISim can be launched using the ISE Project Navigator by first

creating an ISE project for the tutorial design. We will then set some behavioral simulation

properties and launch the ISim simulator to perform a behavioral simulation of the design.

Creating a Project in ISE Project Navigator

We will use the New Project Wizard in ISE Project Navigator to quickly create an ISE

project for the tutorial design.

Note:

Read Installing the Tutorial Design Files to obtain the files required for this design.

Using New Project Wizard

Follow these steps to create an ISE project using the New Project Wizard.

1. Launch the ISE Project Navigator by double-clicking on the Xilinx ISE 11 desktop icon.

Table 2-1: Desired Output Frequency and Multiplier/Divider Parameters Used For

Each Test

Test Freq. (MHz) Period (ps) Multiplier (M) Divider (D)

17513,3323 4

2 120 8,332 6 5

3 250 4000 5 2

4 400 2,500 4 1

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