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Optical Switching and Networking
journal homepage: www.elsevier.com/locate/osn
A novel IP-core mapping algorithm in reliable 3D optical network-on-chips
Lei Guo, Yifan Ge, Weigang Hou
⁎
, Pengxing Guo
⁎
, Qing Cai, Jingjing Wu
School of Computer Science and Engineering, Northeastern University, Shenyang 110819, China
ARTICLE INFO
Keywords:
3D ONoC
IP-core mapping
Reliability
Genetic and simulated annealing algorithm
ABSTRACT
The Optical Network-on-Chip (ONoC) is considered as a promising way to achieve high performance of
multiprocessor systems, and it will be a 3-Dimensional (3D) architecture organized by a certain topology where
optical routers are optically interconnected with each other. For the design of 3D ONoCs, the highly reliable IP-
core mapping is a key problem of properly assigning IP cores onto optical routers for a given communication
task, and it has two main challenges: reliability estimation and mapping scheme. As for reliability estimation,
crosstalk noise and thermal sensitivity which severely influence Signal-Noise-Ratio (SNR) should be measured.
In addition, although standard genetic algorithms have been widely utilized to solve the optimal mapping
solution due to the superiority of simple process, there are some deficiencies such as premature convergence
and inferior local searching. In this paper, the impact factors of ONoC reliability are measured by SNR and
thermal models, and we also design a novel IP-core mapping algorithm called as CGSA (Cataclysm Genetic-
based Simulated Annealing) based on proposed models. In CGSA, we integrate genetic with an improved
simulated annealing algorithm assorted with cataclysm strategies, in order to speed up the searching process.
Furthermore, to enhance the network reliability, CGSA is bound with the topology selection, i.e., CGSA
generates the optimal mapping solution with the best matched 3D ONoC topology. Simulation results show that
CGSA is eff ective on achieving the higher reliability than benchmarks.
1. Introduction
The integration of many hardware functions and software routines
on a single silicon chip becomes the development trend of electronic
systems [1]. However, the Network-on-Chip (NoC) component has
suffered from severe performance bottleneck in terms of high power
consumption, transmission delay, and low bandwidth provisioning, as
predicted by the ITRS roadmap. Therefore, the Optical Network-on-
Chip (ONoC) is proposed as promising communication architecture for
the future multiprocessor systems [2–4].
To systematically solve the problem caused by the bus architecture,
ONoCs transplant computer network technology into the design of
chips based on optical interconnections. Silicon photonics has become
one of the most promising photonic integration platforms, which also
promotes the development of ONoCs. Most importantly, the optical
interconnection of silicon photonics has incomparable advantages of
high bandwidth provisioning as well as low power dissipation and
transmission delay. On the other hand, the 3-Dimensional (3D)
integrated circuit is an attractive solution to overcoming the barriers
to decreasing an interconnection scale [5]. To combine the advantages
of optical interconnection and 3D integration, researchers proposed the
concept of 3D ONoCs, i.e., a 3D architecture organized by a certain
topology where optical routers are optically interconnected with each
other. Compared with traditional 2D structures, 3D ONoC further
reduces the physical connection length between a pair of chip lines,
thus leading to the shorter transmission distance, the smaller trans-
mission delay, and the lower power consumption [2–4].
IP-core mapping is a key problem when we design 3D ONoCs, and
it has a significant influence on the network performance. IP-core
mapping refers to the process of properly assigning IP cores onto
optical routers for a given communication task. In general, IP-core
mapping mainly contains two steps, as shown in Fig. 1. In step 1, the
mapping solution generates using a mapping algorithm, and then it will
be evaluated according to an estimation model in step 2, and feedback
to step 1 for the solution optimizing adjustment [6]. Repeat two steps
until the upper limit. Obviously, there are two main challenges of IP-
core mapping in 3D ONoCs: mapping scheme and estimation model.
From the aspect of mapping schemes, genetic algorithms (GAs)
were widely used to find mapping solutions for NoCs [7–9], but they
merely considered a predefined topology and a single optimization
objective. The authors in [7] proposed a multi-objective GA-based
algorithm that not only jointly optimized power consumption, trans-
mission delay, and chip area but also combined the optimal mapping
solution with the topology selection. However, this approach is
http://dx.doi.org/10.1016/j.osn.2017.08.001
Received 25 May 2016; Received in revised form 17 July 2017; Accepted 8 August 2017
⁎
Correspondence to: School of Computer Science and Engineering Northeastern University, P. O. Box 365, Shenyang 110819, China.
E-mail addresses: houweigang@cse.neu.edu.cn (W. Hou), starguo@stumail.neu.edu.cn (P. Guo).
Optical Switching and Networking 27 (2018) 50–57
Available online 22 August 2017
1573-4277/ © 2017 Elsevier B.V. All rights reserved.
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