Description NANDxxGAH0P
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1 Description
The NANDxxGAH0P is an embedded flash memory storage solution with MultiMediaCard™
interface (eMMC
™). The eMMC™ was developed for universal low-cost data storage and
communication media. The NANDxxGAH0P is fully compatible with MMC bus and hosts.
The NANDxxGAH0P communications are made through an advanced 13-pin bus. The bus
can be either 1-bit, 4-bit, or 8-bit in width. The device operates in high-speed mode at clock
frequencies equal to or higher than 20 MHz, which is the MMC standard. The
communication protocol is defined as a part of this MMC standard and referred to as
MultiMediaCard mode.
The device is designed to cover a wide area of applications such as smart phones,
cameras, organizers, PDA, digital recorders, MP3 players, pagers, electronic toys, etc. They
feature high performance, low power consumption, low cost and high density.
To meet the requirements of embedded high density storage media and mobile applications,
the NANDxxGAH0P supports both 3.3 V supply voltage (V
CC
), and 1.8 V/3.3 V input/output
voltage (V
CCQ
).
The address argument for the NAND16GAH0P is the byte address, while the address
argument for the NAND32GAH0P and NAND64GAH0P is the sector address (512-byte
sectors). This means that the NAND32GAH0P and NAND64GAH0P are not backward
compatible with devices of density lower than 2 Gbytes. If the host does not indicate its
capability of handling sector type of addressing to the memory, the NAND32GAH0P and
NAND64GAH0P change their state to inactive.
The device has a built-in intelligent controller which manages interface protocols, data
storage and retrieval, wear leveling, bad block management, garbage collection, and
internal ECC.
The NANDxxGAH0P makes available to the host sudden power failure safe-update
operations for the data content, by supporting reliable write features.
The device supports boot operation and sleep/awake commands. In particular, during the
sleep state the host power regulator for V
CC
can be switched off, thus minimizing the power
consumption of the NANDxxGAH0P.
The password protection feature can be disabled permanently by setting the permanent
password disable bit in the extended CSD
(PERM_PSWD_DIS bit in the EXT_CSD byte
[171], see Section 7.4: Extended CSD register). It is recommended to disable the password
protection feature on the card, if it is not required. In this way the protection feature can not
be set unintentionally or maliciously.
In addition to the standard Erase command, the NANDxxGAH0P devices feature optional
Secure Erase command, trim operation, and secure trim operation.
The Secure Erase command allows the applications with tight security constraints, to
request that the device performs secure operations even though a negative impact on the
erase time performance is possible.
The trim operation is similar to the standard erase operation, but it applies to write blocks
instead of erase groups. The secure trim operation is similar to the secure erase operation,
but it performs a secure purge operation on write blocks instead of erase groups.
The system performance and characteristics are given in Table 2, Table 3, and Table 4.
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