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S3C2440A MICROCONTROLLER xix
Table of Contents (Continued)
Chapter 23 Camera Interface
Overview .............................................................................................................................................23-1
Features .....................................................................................................................................23-1
Block Diagram ............................................................................................................................23-2
Timing Diagram ...........................................................................................................................23-3
Camera Interface Operation ..................................................................................................................23-5
Two DMA Paths ..........................................................................................................................23-5
Clock Domain .............................................................................................................................23-5
Frame Memory Hirerarchy ............................................................................................................23-6
Memory Storing Method...............................................................................................................23-8
Timing Diagram for Register Setting ..............................................................................................23-9
Timing Diagram for Last IRQ.........................................................................................................23-10
Camera Interface Special Registers.......................................................................................................23-11
Source Format Register ...............................................................................................................23-11
Window Option Register...............................................................................................................23-12
Global Control Register ................................................................................................................23-13
Y1 Start Address Register............................................................................................................23-13
Y2 Start Address Register............................................................................................................23-13
Y3 Start Address Register............................................................................................................23-14
Y4 Start Address Register............................................................................................................23-14
CB1 Start Address Register .........................................................................................................23-14
CB2 Start Address Register .........................................................................................................23-14
CB3 Start Address Register .........................................................................................................23-15
CB4 Start Address Register .........................................................................................................23-15
CR1 Start Address Register .........................................................................................................23-15
CR2 Start Address Register .........................................................................................................23-15
CR3 Start Address Register .........................................................................................................23-16
CR4 Start Address Register .........................................................................................................23-16
Codec Target Format Register ......................................................................................................23-17
Codec Dma Control Register ........................................................................................................23-19
Register Setting Guide for Codec Scaler and Preview Scaler ...........................................................23-20
Codec Pre-Scaler Control Register 1.............................................................................................23-21
Codec Pre-Scaler Control Register 2.............................................................................................23-21
Codec Main-Scaler Control Register..............................................................................................23-22
Codec Dma Target Area Register..................................................................................................23-22
Codec Status Register.................................................................................................................23-23
RGB1 Start Address Register.......................................................................................................23-23
RGB2 Start Address Register.......................................................................................................23-23
RGB3 Start Address Register.......................................................................................................23-24
RGB4 Start Address Register.......................................................................................................23-24
Preview Target Format Register ....................................................................................................23-24
Preview DMA Control Register ......................................................................................................23-25