Design of a WSI Scale Parallel Processor for Intelligent Robot
Control Based on a Dynamic Reconfiguration of Multi-Operand
Arithmetic Units
Yoshichika Fujioka and Nobuhiro Tomabechi
Department of System and Information Engineering, Hachinohe Institute of Technology, H achinohe, Japan 031-8501
SUMMARY
A restructurable (reconfigurable) parallel VLSI
processor designed to minimize the operation delay time
which can be generally used for various operations neces -
sary for controlling an intelligent robot was proposed pre-
viously by the authors. This processor is constructed by
connecting a number of processor elements (PEs) in paral-
lel under the assumption that one PE is integrated with one
VLSI chip. In contrast to this, a method for constructing a
highly integrated processor by integrating several tens to
100 PEs on a single WSI is investigated in this paper. First,
a method for constructing multiple buses efficiently which
move a multiple number of integrated PEs effectively is
proposed. In addition, a method for constructing a defect-
salvaging system utilizing the restructurable parallel archi -
tecture by incorporating a defect-salvaging configuration as
a measure against the yield decrease of WSI is proposed.
As a result of designing a restructurable parallel processor
based on the methods proposed, it has been clarified that a
WSI scale highly integrated processor with 102 PEs piled
up can be constructed with only 35% of the chip surface
increase with the incorporation of the defect-salvaging
configuration. © 2000 Scripta Technica, Syst Comp Jpn,
31(12): 3342, 2000
Key words: Dynamic reconfiguration; WSI; defect
salvaging; intelligent robot; minute operational delay time.
1. Introduction
In order to realize an intelligent robot capable of
autonomous operations, various kinds of processing from
the recognition of the external environment to the flexible
manipulator control are necessary. Since sensor feedback
operations are performed frequently and the flow of infor-
mation is in series in this series of processing, developing
a processor in which the operation delay time from the time
a sensor signal is inputted to the time the control output is
calculated is small has become important [14].
The authors have previously proposed a recon-
figurable parallel VLSI processor designed to minimize
the operation delay time [57]. Since this parallel processor
is made to be capable of restructuring the multiple input
product sum operator of a desired number of inputs by
switching dynamically the direct connection between a
multiplier and an adder for each operational step, it has
advantages in that spatial parallel processing of the multiple
input product sum operation of various kinds of numbers
of input is possible with a small communications overhead
and that the operational efficiency can be improved almost
in proportion to the number of processor elements (PEs).
Thus, this parallel processor comprising several tens to
several hundreds of PEs is considered to be useful for
integrated, high-speed, and flexible control of the mecha-
© 2000 Scripta Technica
Systems and Computers in Japan, Vol. 31, No. 12, 2000
Translated from Denshi Joho Tsushin Gakkai Ronbunshi, Vol. J82-D-I, No. 4, April 1999, pp. 543551
Contract grant sponsor: 1996 and 1997 Science Research Funds of the
Ministry of Education of Japan (Basic Research C).
33