1.2 Thesis Objective
The objective of this thesis is to explore the design of the decoder’s first step, the video
stream parser, with a focus on providing an architecture to be targeted for two ASICs and an
FPGA. While existing implementations have shown to be valuable, the results of targeting
these designs for different platforms has yet to be studied. As a result of the thesis work
presented here, when an H.264/AVC video parser design is targeted for two ASIC process
technologies and an FPGA, insight is gained into the impact this decoder component has
across various process technologies and platforms. Since the video parser is composed of
numerous algorithms, the resulting architecture consists of original and leveraged designs,
where many designs were implemented as a Finite State Machine (FSM) and another used
different hardware components than seen in other published works.
The implementation satisfies the Basic H.264/AVC Profile, which can handle tasks such
as entropy decoding, macroblock adaptation of frame and field modes, and parsing differ-
ent slice types. The overall design is shown in Figure 1.1, where the first step is to read
the compressed video stream and parse the Network Abstraction Layer (NAL) units. The
NAL units, which are used to provide a layer of abstraction over the video data, are parsed
individually and various decoding algorithms are invoked, including Basic, Exponential-
Golomb (Exp-Golomb), and Context-Adaptive Variable-Length Coding (CAVLC) decod-
ing, to recover all video data.
The VHDL hardware description language was used to describe an implementation of
the video stream parser. An existing behavioral model of the H.264/AVC decoder assisted
with the creation and validation of the synthesizable VHDL description. Implementing the
design allowed for the analysis of the parser with respect to the timing and hardware com-
plexities. The Xilinx ISE application was used to synthesize the FPGA model, while Syn-
opsys’ Design Compiler performed the synthesis of the lower power ASIC model. Mod-
elSim 6.1a SE was used to test the FPGA implementation, with the presumption that both
models generate the same functionality.
2
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