Lattice Tri-Rate SDI IP Core User's Guide: Complete 2011 Manual

需积分: 10 46 浏览量更新于2024-07-17 收藏 1.2MB PDF 举报

本资源是Lattice Semiconductor Corp.发布的《Tri-Rate Serial Digital Interface (SDI) Physical Layer IP Core用户指南》(IPUG82_01.5, December 2011)，它是一份详细介绍了该公司的高性能SDI接口知识产权(IP)的核心组件的文档。这份手册主要针对的是支持三种数据速率（tri-rate）的SDI物理层设计，旨在帮助工程师理解和使用这款IP核心。首先，"Quick Facts"部分概述了该IP的核心特性，可能包括高带宽支持、低功耗设计、以及对不同视频接口标准如SDI的广泛兼容性。其功能特点包括： 1. **Receiver**：接收器负责从数字信号中解码并解析数据，确保信号质量的稳定接收。 2. **Decoder/Descrambler**：这个模块负责解码来自不同速率源的原始数据，并可能包含信道去交错（descrambling）功能，以便于后续处理。 3. **Word Alignment/TS Detection**：为了正确处理突发（TS, Transport Stream）数据，IP提供精确的字节对齐和突发检测机制。 4. **Rate Detection and Control**：能够识别并适应不同的数据传输速率，确保在多速率环境下顺畅通信。 5. **Format Detection**：用于检测和识别输入信号的帧格式，确保数据包的正确解析。 6. **CRCChecker**：提供了错误检测功能，通过循环冗余校验（CRC）来验证数据的完整性。 7. **XYZ Word Decoder** 和 **LN Decoder**：分别处理特定的编码格式，可能是用于高清视频信号的编解码操作。 8. **VPID Extraction**：用于提取视频源的唯一标识符（VPID），这对于设备间的通信至关重要。 9. **Transmitter**：IP的发送端包括LN编码器、CRC计算、VPID插入以及可能的Scrambler/Encoder，确保信号的正确编码和同步。 10. **Low-Speed Serializer**：用于将数据转换成适合传输的低速序列信号。 11. **Signal Descriptions**：详述了各种接口信号的电气特性，确保与硬件的正确连接。 "Interfacing with Tri-Rate SDI PHY IP Core"章节详细说明了如何将IP与SerDes（serializer/deserializer）接口、板级传输接口以及不同的SDI模式（如10-bit模式和SDLDR模式）进行连接。此外，还涉及VPID的提取和插入，以及针对FPGA的特定配置接口。这份用户指南不仅提供了技术规格和操作指导，也包含了可能遇到的问题和解决方案，是设计和集成SDI高速接口系统时不可或缺的参考资料。在整个过程中，开发者需要注意版权声明和法律条款，确保符合Lattice Semiconductor Corp.的许可协议。

Lattice Semiconductor Functional Description

IPUG82_01.5, December 2011 9 Tri-Rate SDI PHY IP User’s Guide

detection, CRC checker, XYZ word decoder, LN decoder and VPID extraction module. A description of each of

these blocks is given below.

Figure 2-2. Tri-Rate SDI Receiver, High-Level Block Diagram

Decoder/Descrambler

All the interface standards supported by the Tri-Rate SDI PHY IP core specify the same scrambling and encoding

methods. The polynomials used are given in the sub-section on the scrambler. The decoder/descrambler is imple-

mented in the 20-bit parallel path. The input data is first decoded to NRZ and then descrambled following an essen-

tially reverse process of the encoding and scrambling operations.

Word Alignment/TRS Detection

The receiver reads the raw, possibly misaligned parallel data from the SERDES. The word alignment block deter-

mines the degree of misalignment (offset) by looking for the special TRS sequences in the data. TRS is the unique

sequence, 3FFh,000h,000h, in the video stream that marks either the end of active video (EAV) or the start of

active video (SAV) time instants. In HD and 3G Level-A video streams, since two independent video streams are

interleaved, the timing reference sequence to look for is 3FF

, 3FF

, 000

. The TRS for 3G

Level-B video is 3FF

, 3FF

, 000

. Once the offset is deter-

mined, the words are re-aligned using the offset value.

Rate Detection and Control

This module is the heart of the multi-rate SDI receiver infrastructure. Rate detection is the process of determining

the interface standard of the incoming video stream. Rate detection is performed by sequentially scanning the input

for different interface standards. During each rate scan, the receiver identifies the rate that is being scanned

through some output ports, to allow the external modules like the SERDES and clock generator, to be set to that

rate. Once the clock generator and the SERDES are set to a data rate, the receiver tries to receive the signal for

that rate. The receiver checks the TRS instances (number of active words and total words) to see if they are consis-

tent with the source formats for the interface standard that is being received. If they match, the receiver locks to this

Decoder /

Descrambler

Word

Alignment/

TRS

Detection

CRC

Checker

pd_out

y1_crc_error

Rate

Detection/

Control

rxdata

rx_clk

rx_hd_sdn

rx_tg_sdn

Format

Detection

vid_format

rx_rate

vid_active

ln1_out

field

hblank

vblank

trs_out

xyz Word

Decoder

frame_format

eav_error

sav_error

rx_lb_lan

ychannel

c1_crc_error

y2_crc_error

c2_crc_error

ln2_out

vpid1_out

VPID

Extraction

vp1_valid

vp1_cserr

vp1_parerr

vp1_lineok

Lattice Semiconductor Functional Description

IPUG82_01.5, December 2011 10 Tri-Rate SDI PHY IP User’s Guide

video stream and asserts the vid_active signal. On the other hand, if the TRS instances are not consistent with the

source formats that are expected for the current scanned rate, the receiver advances to scan the next rate.

The rate detection state machine is set to scan for the HD rate first, followed by 3G and SD rates and then to go

back to scan HD to start the sequence over. The state machine advances to scan the next rate only if that rate is

enabled by the dynamic input signal rx_rate. For each scan rate, the state machine goes through three states-

“Program”, “Check” and “Lock”. The state advances are based on the number of TRS matches, TRS mismatches

and time-out errors. A time-out error occurs when a TRS is not received in a reasonably long duration of time. Dur-

ing the “Program” state, the external clock sources are set to provide the relevant clocks and/or the SERDES divid-

ers are set to receive the relevant rate. If a TRS is received or if the number of time-out errors is more than the

value set using “3G (HD/SD) Programming time” parameter, the state machine advances to the “Check” state.

While in the “Check” state, if the number of TRS matches reaches the value set for “Lock match threshold” param-

eter, the state machine advances to “Lock” state. On the other hand, if the number of TRS mismatches and time-

out errors exceeds the “Unlock error threshold” value, the state machine advances to the “Check” state for the next

rate. While in the “Lock” state, the state machine continues to be in that state as long the number of time-out and

TRS mismatch errors are within “Unlock error threshold” value. When the number of errors exceeds the threshold

while in the “Lock” state, the state machine advances to the “Check” state for the next rate.

SMPTE 292M and SMPTE 424M also define a fractional frame rate video stream compliant with the North Ameri-

can standards. Thus SMPTE 292M includes a 1.4835 Gbps data rate in addition to the 1.485 Gbps rate and

SMPTE 424M includes a 2.967 Gbps data rate in addition to the 2.97 Gbps rate. This IP core supports both the

integer and fractional frame rates, as long as the data and clock inputs to the IP core are consistent with the corre-

sponding rates. While the IP core can receive both integer and fractional frame rate standards, it will not be able to

distinguish between the two. However, integer or fractional frame rate standards can be easily determined by con-

structing a small logic circuit outside the IP to compare the frequency of the receive recovered clock with that of

another clock of known frequency (like the receive reference clock or the 100 MHz clock available on the

LatticeECP3 Video Protocol Board).

Format Detection

This module determines the source format of the input video stream. The format is based on the number of active

words, number of total words and whether the video is interlaced. The format is provided through the vid_format

and frame_format output ports. For 3G Level-B video (3G-b), the stream 1 video data is used for format detection.

CRC Checker

The CRC checker computes the CRC values for each of the video streams and components and compares those

with the CRC values available in CR0 and CR1 words of the received video. In HD and 3G Level-A video (3G-a)

streams, there are two CRC words per line that contain the CRC value for the previous line. The CRC checker com-

putes the CRC for each line, compares with the received CRC and flags an error if there is a mismatch. For 3G-b,

there are four CRC words, one each for the Y and C components of each stream. Errors are flagged separately for

each of the four CRC comparisons.

XYZ Word Decoder

This block decodes the “XYZ” word that follows the TRS in the video stream. By decoding the XYZ word, the video

timing signals field, hblank (horizontal blanking) and vblank (vertical blanking) are determined. XYZ word is also

used to determine whether the TRS corresponds to an EAV or a SAV instant.

LN Decoder

In HD and 3G video formats, the line number is encoded as a two-word sequence and inserted after the XYZ word

of the EAV sequence. The LN decoder block decodes the line number from the LN double words and gives out the

line number value on the ln1_out port. For 3G-b, the line numbers for stream 1 and stream 2 video are separately

given out on ln1_out and ln2_out ports respectively.

Lattice Semiconductor Functional Description

IPUG82_01.5, December 2011 11 Tri-Rate SDI PHY IP User’s Guide

VPID Extraction

The VPID extraction module extracts the video payload information (SMPTE 352M [11]) embedded in the HANC

part of the video stream. In addition to the VPID bytes, this module also provides some error and status signals.

The status signal vp1_valid indicates whether the last received VPID information was valid and the signal

vp1_lineok indicates if the VPID was available in the appropriate line numbers for the received format. The error

signals vp1_cserr and vp1_parerr are used to denote the checksum error and parity error respectively.

Transmitter

The transmitter supports dynamic multi-rate operation catering to SD, HD and 3G standards. The transmit rate is

set through the input ports, hd_sdn_in and lb_lan_in as well by the frequency of pdi_clk. The transmitter and

receiver are independent of each other and each can be used to transport any rate or format. A high-level block

diagram of the transmitter is shown in Figure 2-3.

Figure 2-3. Multi-Rate SDI Transmitter, High-Level Block Diagram

The input data to the transmitter is SMPTE-formatted parallel video data, which typically includes active video,

blanking, ANC (Ancillary), and TRS words. If the CRC and line number (LN) words for HD/3G are available in the

video stream, the IP core can pass them on. If the CRC and/or LN information is not available from the stream, the

IP can fill them in and insert them in the stream at the right places. The transmitter is comprised of the following

logical modules: LN encoder, CRC computation, VPID insertion, LN/CRC insertion, scrambler/encoder and low-

speed serializer. A brief description of each of these modules is given below.

LN Encoder

The LN encoder converts the raw line number value read from the input port to two LN words for insertion in the

video stream. This module is used only for HD/3G inputs. This module is optional and used only when the LN

words are not already available in the video data stream. For 3G-b video, there are two line number input ports,

ln1_in and ln2_in, one for each of the two 3G-b video streams.

CRC Computation

The CRC computation module is optionally added if the CRC insertion option is enabled through the IP GUI. The

CRC is computed separately for each Y and C component of the entire active line, encoded to two CRC words per

component and embedded at the appropriate places in the next line. For 3G-b streams, there are four separate

Scrambler

/ Encoder

LN/CRC Insertion

CRC

Computation

pd_in

trs_in

pdi_clk

txdata

txd_ldr

Low-

Speed

Serializer

Encoder

ln2_in

ln2_set

sd8b_mode

hd_sdn_in

ln1_in

ln1_set

lb_lan_in

Scrambler

/ Encoder

video8b

pd_in_sd

VPID

insertion

vpid2_in

vpid1_in

剩余50页未读，继续阅读

xh_24

粉丝: 98
资源: 12

Lattice Tri-Rate SDI IP Core User's Guide: Complete 2011 Manual

telnet-0.17-65.el7_8.x86_64.rpm

Tri-net.zip

完善代码：import math class Triangle: def __init__(self, a, b, c): self.__a = a self.__b = b self.__c = c def get_area(self): h = (self.__a+self.__b+self.__c)/2 s = math.sqrt(h*(h-self.__a)*(h-self.__b)*(h-self.__c)) print(f'三角形的面积：{s}') tri = Triangle(3, 4, 5)

矩阵对角线相关计算2 - lower.tri, upper.tri

c++红枣Delaunay三角剖分算法代码

TRI-CORE 系

如何在yolov7中使用Tri-Layer插件

最新资源

完善代码：import math class Triangle: def init(self, a, b, c): self.a = a self.b = b self.__c = c def get_area(self): h = (self.a+self.b+self.c)/2 s = math.sqrt(h(h-self.a)(h-self.b)*(h-self.c)) print(f'三角形的面积：{s}') tri = Triangle(3, 4, 5)