MIPS32指令集详解：程序员指南

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"MIPS程序员指南卷II-A 指令集详解，PDF版，涵盖了MIPS32架构的指令集细节，由MIPSTech, LLC (现为Wave Computing公司的一部分) 出版，详细介绍了MIPS处理器的编程原理和技术。" 在计算机体系结构中，MIPS（Microprocessor without Interlocked Pipeline Stages）是一种精简指令集计算机(RISC)架构，广泛用于教学、嵌入式系统以及早期的高性能计算。《MIPS程序员指南卷II-A》是深入理解MIPS32指令集的重要参考资料，它旨在帮助程序员和硬件设计师更好地理解和利用MIPS32处理器的特性。文档编号MD00086，修订至5.04版，发布于2013年12月11日，详细阐述了MIPS32指令集，包括各种数据处理、控制转移、加载/存储以及浮点运算指令。这些指令构成了MIPS处理器的基础，使得开发者能够编写高效的机器代码。 MIPS32指令集包含了以下关键部分： 1. 数据处理指令：如算术运算（加、减、乘、除）、逻辑运算（与、或、异或、取反）以及移位操作，这些指令用于处理数据并进行基本的算术和逻辑操作。 2. 控制转移指令：如跳转（J, jal）、条件分支（beq, bne等），以及循环控制指令（loop, loopne等），这些指令负责程序流程的控制，实现程序的分支和循环。 3. 加载/存储指令：如lw, sw, lb, sb等，用于在寄存器和内存之间移动数据，是内存访问的核心。 4. 浮点运算指令：针对浮点数的运算，包括加、减、乘、除以及比较等，对于需要处理浮点计算的科学计算和图形应用尤其重要。 5. 系统相关指令：如mfc0, mtc0等，用于访问和设置处理器的控制寄存器，进行系统级的配置和管理。 6. 同步原语：如sync，用于实现多处理器环境中的数据一致性。此指南还可能涵盖了指令编码、异常处理、中断机制以及向量浮点扩展（如VFPU）等内容，以帮助开发者编写高效的MIPS32汇编代码。同时，由于MIPS架构在Linux系统中也有广泛应用，因此，了解MIPS指令集对于开发和调试MIPS平台上的Linux应用程序也是至关重要的。请注意，文档中的信息受美国及其它国家的版权法保护，并且可能包含专有信息。未经MIPS或其关联公司的书面许可，不得复制、修改或分发该信息，违反者可能面临法律制裁。对于源格式提供的文档，如FrameMaker或Microsoft Word格式的文档，还有额外的使用和分发限制。

1.3 Special Symbols in Pseudocode Notation

MIPS® Architecture For Programmers Volume II-A: The MIPS32® Instruction Set, Revision 5.04 16

• UNPREDICTABLE operations must not halt or hang the processor

1.2.2 UNDEFINED

UNDEFINED operations or behavior may vary from processor implementation to implementation, instruction to

instruction, or as a function of time on the same implementation or instruction. UNDEFINED operations or behavior

may vary from nothing to creating an environment in which execution can no longer continue. UNDEFINED opera-

tions or behavior may cause data loss.

UNDEFINED operations or behavior has one implementation restriction:

• UNDEFINED operations or behavior must not cause the processor to hang (that is, enter a state from which

there is no exit other than powering down the processor). The assertion of any of the reset signals must restore

the processor to an operational state

1.2.3 UNSTABLE

UNSTABLE results or values may vary as a function of time on the same implementation or instruction. Unlike

UNPREDICTABLE values, software may depend on the fact that a sampling of an UNSTABLE value results in a

legal transient value that was correct at some point in time prior to the sampling.

UNSTABLE values have one implementation restriction:

• Implementations of operations generating UNSTABLE results must not depend on any data source (memory or

internal state) which is inaccessible in the current processor mode

1.3 Special Symbols in Pseudocode Notation

In this book, algorithmic descriptions of an operation are described as pseudocode in a high-level language notation

resembling Pascal. Special symbols used in the pseudocode notation are listed in Table 1.1.

Table 1.1 Symbols Used in Instruction Operation Statements

Symbol Meaning

← Assignment

=, ≠ Tests for equality and inequality

|| Bit string concatenation

A y-bit string formed by y copies of the single-bit value x

b#n A constant value n in base b. For instance 10#100 represents the decimal value 100, 2#100 represents the

binary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). If the "b#"

preﬁx is omitted, the default base is 10.

0bn A constant value n in base 2. For instance 0b100 represents the binary value 100 (decimal 4).

0xn A constant value n in base 16. For instance 0x100 represents the hexadecimal value 100 (decimal 256).

y z

Selection of bits y through z of bit string x. Little-endian bit notation (rightmost bit is 0) is used. If y is less

than z, this expression is an empty (zero length) bit string.

+, − 2’s complement or ﬂoating point arithmetic: addition, subtraction

About This Book

17 MIPS® Architecture For Programmers Volume II-A: The MIPS32® Instruction Set, Revision 5.04

*, × 2’s complement or ﬂoating point multiplication (both used for either)

div 2’s complement integer division

mod 2’s complement modulo

/ Floating point division

< 2’s complement less-than comparison

> 2’s complement greater-than comparison

≤ 2’s complement less-than or equal comparison

≥ 2’s complement greater-than or equal comparison

nor Bitwise logical NOR

xor Bitwise logical XOR

and Bitwise logical AND

or Bitwise logical OR

not Bitwise inversion

&& Logical (non-Bitwise) AND

<< Logical Shift left (shift in zeros at right-hand-side)

>> Logical Shift right (shift in zeros at left-hand-side)

GPRLEN The length in bits (32 or 64) of the CPU general-purpose registers

GPR[x] CPU general-purpose register x. The content of GPR[0] is always zero. In Release 2 of the Architecture,

GPR[x] is a short-hand notation for SGPR[ SRSCtl

CSS

, x].

SGPR[s,x] In Release 2 of the Architecture and subsequent releases, multiple copies of the CPU general-purpose regis-

ters may be implemented. SGPR[s,x] refers to GPR set s, register x.

FPR[x] Floating Point operand register x

FCC[CC] Floating Point condition code CC. FCC[0] has the same value as COC[1].

FPR[x] Floating Point (Coprocessor unit 1), general register x

CPR[z,x,s] Coprocessor unit z, general register x, select s

CP2CPR[x] Coprocessor unit 2, general register x

CCR[z,x] Coprocessor unit z, control register x

CP2CCR[x] Coprocessor unit 2, control register x

COC[z] Coprocessor unit z condition signal

Xlat[x] Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR number

BigEndianMem Endian mode as conﬁgured at chip reset (0 →Little-Endian, 1 → Big-Endian). Speciﬁes the endianness of

the memory interface (see LoadMemory and StoreMemory pseudocode function descriptions), and the endi-

anness of Kernel and Supervisor mode execution.

BigEndianCPU The endianness for load and store instructions (0 → Little-Endian, 1 → Big-Endian). In User mode, this

endianness may be switched by setting the RE bit in the Status register. Thus, BigEndianCPU may be com-

puted as (BigEndianMem XOR ReverseEndian).

ReverseEndian Signal to reverse the endianness of load and store instructions. This feature is available in User mode only,

and is implemented by setting the RE bit of the Status register. Thus, ReverseEndian may be computed as

(SR

and User mode).

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning

1.3 Special Symbols in Pseudocode Notation

MIPS® Architecture For Programmers Volume II-A: The MIPS32® Instruction Set, Revision 5.04 18

LLbit Bit of virtual state used to specify operation for instructions that provide atomic read-modify-write. LLbit is

set when a linked load occurs and is tested by the conditional store. It is cleared, during other CPU operation,

when a store to the location would no longer be atomic. In particular, it is cleared by exception return instruc-

tions.

I:,

I+n:,

I-n:

This occurs as a preﬁx to Operation description lines and functions as a label. It indicates the instruction

time during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the current

instruction appear to occur during the instruction time of the current instruction. No label is equivalent to a

time label of I. Sometimes effects of an instruction appear to occur either earlier or later — that is, during the

instruction time of another instruction. When this happens, the instruction operation is written in sections

labeled with the instruction time, relative to the current instruction I, in which the effect of that pseudocode

appears to occur. For example, an instruction may have a result that is not available until after the next

instruction. Such an instruction has the portion of the instruction operation description that writes the result

The effect of pseudocode statements for the current instruction labelled I+1 appears to occur “at the same

time” as the effect of pseudocode statements labeled I for the following instruction. Within one pseudocode

sequence, the effects of the statements take place in order. However, between sequences of statements for

different instructions that occur “at the same time,” there is no deﬁned order. Programs must not depend on a

particular order of evaluation between such sections.

PC The Program Counter value. During the instruction time of an instruction, this is the address of the instruc-

tion word. The address of the instruction that occurs during the next instruction time is determined by assign-

ing a value to PC during an instruction time. If no value is assigned to PC during an instruction time by any

pseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit MIPS16e instruc-

tion) or 4 before the next instruction time. A taken branch assigns the target address to the PC during the

instruction time of the instruction in the branch delay slot.

In the MIPS Architecture, the PC value is only visible indirectly, such as when the processor stores the

restart address into a GPR on a jump-and-link or branch-and-link instruction, or into a Coprocessor 0 register

on an exception. The PC value contains a full 32-bit address all of which are signiﬁcant during a memory ref-

erence.

ISA Mode In processors that implement the MIPS16e Application Speciﬁc Extension or the microMIPS base architec-

tures, the ISA Mode is a single-bit register that determines in which mode the processor is executing, as fol-

lows:

In the MIPS Architecture, the ISA Mode value is only visible indirectly, such as when the processor stores a

combined value of the upper bits of PC and the ISA Mode into a GPR on a jump-and-link or branch-and-link

instruction, or into a Coprocessor 0 register on an exception.

PABITS The number of physical address bits implemented is represented by the symbol PABITS. As such, if 36

physical address bits were implemented, the size of the physical address space would be 2

PABITS

bytes.

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning

Encoding Meaning

0 The processor is executing 32-bit MIPS instructions

1 The processor is executing MIIPS16e or microMIPS

instructions

About This Book

19 MIPS® Architecture For Programmers Volume II-A: The MIPS32® Instruction Set, Revision 5.04

1.4 For More Information

Various MIPS RISC processor manuals and additional information about MIPS products can be found at the MIPS

URL: http://www mips.com

For comments or questions on the MIPS32® Architecture or this document, send Email to support@mips.com.

FP32RegistersMode Indicates whether the FPU has 32-bit or 64-bit ﬂoating point registers (FPRs). In MIPS32 Release 1, the FPU

has 32 32-bit FPRs in which 64-bit data types are stored in even-odd pairs of FPRs. In MIPS64, (and option-

ally in MIPS32 Release2 and MIPSr3) the FPU has 32 64-bit FPRs in which 64-bit data types are stored in

any FPR.

In MIPS32 Release 1 implementations, FP32RegistersMode is always a 0. MIPS64 implementations have a

compatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. In

such a case FP32RegisterMode is computed from the FR bit in the Status register. If this bit is a 0, the pro-

cessor operates as if it had 32 32-bit FPRs. If this bit is a 1, the processor operates with 32 64-bit FPRs.

The value of FP32RegistersMode is computed from the FR bit in the Status register.

InstructionInBranchDe-

laySlot

Indicates whether the instruction at the Program Counter address was executed in the delay slot of a branch

or jump. This condition reﬂects the dynamic state of the instruction, not the static state. That is, the value is

false if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but which

is not executed in the delay slot of a branch or jump.

SignalException(excep-

tion, argument)

Causes an exception to be signaled, using the exception parameter as the type of exception and the argument

parameter as an exception-speciﬁc argument). Control does not return from this pseudocode function—the

exception is signaled at the point of the call.

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning

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