AT45DB161D-su存储芯片技术规格与特性详解

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"AT45DB161D-su是一款存储芯片，其数据手册提供了详细的技术规格和功能。这款芯片适用于需要高速、低功耗、安全存储解决方案的应用场景。" AT45DB161D-su是一款由Atmel公司生产的串行闪存存储器，它具有高速、低功耗和多种擦写选项的特点。该芯片支持两种电压范围：2.5V-3.6V或2.7V-3.6V，确保在各种电源条件下稳定工作。其RapidS™串行接口设计允许最高66MHz的时钟频率，兼容SPI（串行外围设备接口）的模式0和3，提供快速的数据传输。该芯片的一大特色是用户可配置的页面大小，可以选择512字节或528字节每页。这种灵活性使得用户可以根据应用需求优化存储性能。同时，芯片内置的智能编程操作支持4,096个页面（每个页面512/528字节），主内存容量达到16Mbits。 AT45DB161D-su提供了灵活的擦除选项，包括页擦除（512字节）、块擦除（4K字节）、扇区擦除（128K字节）和全芯片擦除（16Mbits）。这使得用户可以针对不同大小的数据进行精细化的管理。为了提高效率，该芯片配备了两个512/528字节的SRAM数据缓冲器。这使得在重新编程闪存阵列的同时可以接收新的数据，实现了数据处理和存储的并行操作。连续读取能力则使得在整个数组中进行无缝读取成为可能，非常适合代码阴影应用。低功耗是AT45DB161D-su的另一大亮点。在活动读取模式下，典型电流仅为7mA；待机状态下，典型电流仅为25μA；而深度休眠模式下，电流降低到15μA，这在便携式和电池供电设备中尤为重要。此外，该芯片还具备硬件和软件数据保护特性。每个扇区都可以单独锁定，确保代码和数据的安全存储。一个128字节的安全寄存器包含64字节的用户可编程空间和64字节的唯一设备标识符，增强了安全性。JEDEC标准的制造商和设备ID读取功能则方便了识别和验证芯片。最后，AT45DB161D-su的编程/擦除周期高达100,000次，保证了其在频繁写入操作的应用中的耐用性。这款存储芯片广泛应用于嵌入式系统、物联网设备、汽车电子等领域，为需要高效、安全存储的系统提供了理想的解决方案。

3500P–DFLASH–5/2013

AT45DB161D

page address bits (A20 - A9) that specify the page in the main memory to be erased and nine don’t care bits. When

a low-to-high transition occurs on the

CS pin, the part will erase the selected page (the erased state is a logical 1).

The erase operation is internally self-timed and should take place in a maximum time of t

. During this time, the

status register and the RDY/BUSY pin will indicate that the part is busy.

7.5 Block Erase

A block of eight pages can be erased at one time. This command is useful when large amounts of data has to be

written into the device. This will avoid using multiple Page Erase Commands. To perform a block erase for the

standard DataFlash page size (528-bytes), an opcode of 50H must be loaded into the device, followed by three

address bytes comprised of two don’t care bits, nine page address bits (PA11 -PA3) and 13 don’t care bits. The

nine page address bits are used to specify which block of eight pages is to be erased. To perform a block erase for

the binary page size (512-bytes), the opcode 50H must be loaded into the device, followed by three address bytes

consisting of three don’t care bits, nine page address bits (A20 - A12) and 12 don’t care bits. The nine page

address bits are used to specify which block of eight pages is to be erased. When a low-to-high transition occurs

on the

CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed and

should take place in a maximum time of t

. During this time, the status register and the RDY/BUSY pin will

indicate that the part is busy.

Table 7-1. Block Erase Addressing

7.6 Sector Erase

The Sector Erase command can be used to individually erase any sector in the main memory. There are 16

sectors and only one sector can be erased at one time. To perform sector 0a or sector 0b erase for the standard

DataFlash page size (528-bytes), an opcode of 7CH must be loaded into the device, followed by three address

bytes comprised of two don’t care bits, nine page address bits (PA11 - PA3) and 13 don’t care bits. To perform a

sector 1-15 erase, the opcode 7CH must be loaded into the device, followed by three address bytes comprised of

two don’t care bits, four page address bits (PA11 - PA8) and 18 don’t care bits. To perform sector 0a or sector 0b

erase for the binary page size (512-bytes), an opcode of 7CH must be loaded into the device, followed by three

address bytes comprised of three don’t care bit and nine page address bits (A20 - A12) and 12 don’t care bits. To

perform a sector 1-15 erase, the opcode 7CH must be loaded into the device, followed by three address bytes

comprised of 3 don’t care bit and four page address bits (A20 - A17) and 17 don’t care bits. The page address bits

are used to specify any valid address location within the sector which is to be erased. When a low-to-high transition

occurs on the CS pin, the part will erase the selected sector. The erase operation is internally self-timed and should

PA11/

A20

PA10/

A19

PA9/

A18

PA8/

A17

PA7/

A16

PA6/

A15

PA5/

A14

PA4/

A13

PA3/

A12

PA2/

A11

PA1/

A10

PA0/

A9 Block

000000000XXX 0

000000001XXX 1

000000010XXX 2

000000011XXX 3

•

111111100XXX 508

111111101XXX 509

111111110XXX 510

111111111XXX 511

3500P–DFLASH–5/2013

AT45DB161D

7.8 Main Memory Page Program Through Buffer

This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase

operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI) and then programmed into a

specified page in the main memory. To perform a main memory page program through buffer for the standard

DataFlash page size (528-bytes), a 1-byte opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into

the device, followed by three address bytes. The address bytes are comprised of two don’t care bits, 12 page

address bits, (PA11 - PA0) that select the page in the main memory where data is to be written, and 10 buffer

address bits (BFA9 - BFA0) that select the first byte in the buffer to be written. To perform a main memory page

program through buffer for the binary page size (512-bytes), the opcode 82H for buffer 1 or 85H for buffer 2, must

be clocked into the device followed by three address bytes consisting of three don’t care bits, 12 page address bits

(A20 - A9) that specify the page in the main memory to be written, and 9 buffer address bits (BFA8 - BFA0) that

selects the first byte in the buffer to be written. After all address bytes are clocked in, the part will take data from the

input pins and store it in the specified data buffer. If the end of the buffer is reached, the device will wrap around

back to the beginning of the buffer. When there is a low-to-high transition on the

CS pin, the part will first erase the

selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. Both

the erase and the programming of the page are internally self-timed and should take place in a maximum time of

. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy.

8. Sector Protection

Two protection methods, hardware and software controlled, are provided for protection against inadvertent or

erroneous program and erase cycles. The software controlled method relies on the use of software commands to

enable and disable sector protection while the hardware controlled method employs the use of the Write Protect

(WP) pin. The selection of which sectors that are to be protected or unprotected against program and erase

operations is specified in the nonvolatile Sector Protection Register. The status of whether or not sector protection

has been enabled or disabled by either the software or the hardware controlled methods can be determined by

checking the Status Register.

8.1 Software Sector Protection

8.1.1 Enable Sector Protection Command

Sectors specified for protection in the Sector Protection Register can be protected from program and erase

operations by issuing the Enable Sector Protection command. To enable the sector protection using the software

controlled method, the CS pin must first be asserted as it would be with any other command. Once the CS pin has

been asserted, the appropriate 4-byte command sequence must be clocked in via the input pin (SI). After the last

bit of the command sequence has been clocked in, the CS pin must be deasserted after which the sector

protection will be enabled.

Table 8-1. Enable Sector Protection Command

Figure 8-1. Enable Sector Protection

Command Byte 1 Byte 2 Byte 3 Byte 4

Enable Sector Protection 3DH 2AH 7FH A9H

Opcode

Byte 1

Opcode

Byte 2

Opcode

Byte 3

Opcode

Byte 4

Each transition

represents eight bits

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