LATTICE ECP3 器件系列数据手册：高性能逻辑密度与嵌入式SERDES

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"LATTICE-ECP3-datasheet 是莱迪斯公司(ECP3系列) FPGA 器件的数据手册，提供了该系列的详细技术规格和功能特性。" Lattice ECP3系列是Lattice Semiconductor公司推出的一款高性能现场可编程门阵列(FPGA)，主要特点是具有更高的逻辑密度和集成度，以及内置的SERDES和sysDSP模块，适用于各种高速通信和接口应用。以下是对这些关键特性的详细解释： 1. **更高的逻辑密度**：Lattice ECP3系列提供17K到149K的查找表(LUT)，使得在单个芯片上可以实现更复杂的系统集成。这允许设计者在一个设备中实现更多的功能，减少了系统中的组件数量，从而降低成本并提高可靠性。 2. **嵌入式SERDES**：支持150Mbps到3.2Gbps的速度，用于通用的8b10b、10-bit SERDES和8-bit SERDES模式。对于其他协议，每个通道的数据速率可达230Mbps至3.2Gbps。这一特性使得ECP3能支持多种高速串行接口，如PCI Express、SONET/SDH、以太网（1GbE、SGMII、XAUI）、CPRI、SMPTE 3G和Serial RapidIO，适应了现代通信系统对高带宽的需求。 3. **sysDSP模块**：sysDSP（系统数字信号处理）是一种内建的硬件加速器，拥有完全级联的切片架构，可以提供12到160个切片进行高性能的乘加操作。每个切片配备一个54位的算术逻辑单元(ALU)，支持时间分复用的MAC共享、舍入和截断功能。这种设计旨在加速数字信号处理算法，提高实时处理能力，尤其适合于音频、视频处理和通信系统的应用。 4. **灵活性和可配置性**：Lattice ECP3的另一个优势是其高度的灵活性，可以针对不同的应用需求进行定制。例如，每个sysDSP切片可以配置为半36x36、两个18x18或四个9x9的乘法器，这使得设计者可以根据具体需求选择最适合的计算资源。此外，数据手册还会包含关于电源管理、I/O接口、时钟管理和配置选项等更多详细信息。Lattice Semiconductor Corporation在文档中提醒，所有的规格和信息可能会随时间而改变，用户应访问官方网站获取最新的更新和法律声明。LATTICE-ECP3-datasheet是工程师设计基于Lattice ECP3 FPGA系统时的重要参考资料。

2-13

Architecture

Lattice Semiconductor LatticeECP3 Family Data Sheet

Primary Clock Routing

The purpose of the primary clock routing is to distribute primary clock sources to the destination quadrants of the

device. A global primary clock is a primary clock that is distributed to all quadrants. The clock routing structure in

LatticeECP3 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The pri-

mary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources

are connected to these muxes. Figure 2-12 shows the clock routing for one quadrant. Each quadrant mux is identi-

cal. If desired, any clock can be routed globally.

Figure 2-12. Per Quadrant Primary Clock Selection

Dynamic Clock Control (DCC)

The DCC (Quadrant Clock Enable/Disable) feature allows internal logic control of the quadrant primary clock net-

work. When a clock network is disabled, all the logic fed by that clock does not toggle, reducing the overall power

consumption of the device.

Dynamic Clock Select (DCS)

The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent

input clock sources without any glitches or runt pulses. This is achieved regardless of when the select signal is tog-

gled. There are two DCS blocks per quadrant; in total, there are eight DCS blocks per device. The inputs to the

DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7

(see Figure 2-12).

Figure 2-13 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed

to other modes. For more information about the DCS, please see the list of technical documentation at the end of

this data sheet.

Figure 2-13. DCS Waveforms

CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7

63:1 63:1 63:1 63:1 58:1 58:1 58:1 58:163:1 63:1

DCC DCC DCC DCC DCS DCSDCC DCC

8 Primary Clocks (CLK0 to CLK7) per Quadrant

PLLs + DLLs + CLKDIVs + PCLK PIOs + SERDES Quads

CLK0

SEL

DCSOUT

CLK1

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