200G/400G以太网IEEE 802.3bs标准：MAC与物理层协议详解

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IEEE 802.3bs标准是针对以太网的最新修订版，该标准主要关注于200 Gb/s（两百千兆比特每秒）和400 Gb/s（四百千兆比特每秒）的数据传输速度。这份标准由局域网/城域网标准化委员会（LAN/MAN Standards Committee）发起并赞助，旨在推动高带宽以太网技术的发展，以满足现代数据中心和云计算环境中对高速、低延迟网络的需求。在802.3bs标准中，核心部分包括了媒体访问控制（MAC）层、物理层的PCS（Physical Coding Sublayer，物理编码子层）、PMA（Physical Medium Attachment，物理媒介接入）以及PMD（Physical Medium Dependent，物理媒介依赖）协议。MAC层负责处理数据帧的发送和接收，确保在多个设备之间高效、有序地进行通信。PCS负责将数据信号编码成适合在光纤上传输的形式，保证数据的完整性和可靠性。PMA则定义了信号如何在物理连接（如光纤）上进行传输，包括电气接口规范。最后，PMD负责处理信号在光纤中的传输特性，如波长选择、信号衰减补偿等，以确保信号在长距离传输后仍能保持高质量。这个标准是对先前802.3系列标准的补充和扩展，涵盖了从802.3bw到802.3bz等一系列的增补，这些增补旨在解决高速以太网面临的挑战，如更高的带宽需求、更短的帧结构设计、更有效的功率管理、以及适应不同介质（如铜缆和光纤）的兼容性。 802.3bs标准的发布对于数据中心网络架构的升级至关重要，它允许网络基础设施支持更高效的计算密集型工作负载，并有助于推动云计算和大数据时代的无缝连接。此外，该标准也为未来的1000 Gb/s甚至更高速率的以太网奠定了基础，使得未来网络技术的演进更加清晰明确。 802.3bs标准是当前和未来网络技术发展的关键里程碑，它通过定义新的技术规范，提升了以太网在速度、性能和可扩展性方面的水平，对IT行业的进步起到了推动作用。

45.2.4.11b BASE-R PHY XS test-pattern control register (Register 4.42).............................. 78

45.2.4.11b.1 Transmit test-pattern enable (4.42.3)............................................................ 78

45.2.4.11c Multi-lane BASE-R PHY XS alignment status 1 register (Register 4.50) ............. 78

45.2.4.11c.1 PHY XS lane alignment status (4.50.12)...................................................... 78

45.2.4.11d Multi-lane BASE-R PHY XS alignment status 3 register (Register 4.52) ............. 79

45.2.4.11d.1 Lane 7 aligned (4.52.7) ................................................................................. 79

45.2.4.11d.2 Lane 6 aligned (4.52.6) ................................................................................. 79

45.2.4.11d.3 Lane 5 aligned (4.52.5) ................................................................................. 79

45.2.4.11d.4 Lane 4 aligned (4.52.4) ................................................................................. 80

45.2.4.11d.5 Lane 3 aligned (4.52.3) ................................................................................. 80

45.2.4.11d.6 Lane 2 aligned (4.52.2) ................................................................................. 80

45.2.4.11d.7 Lane 1 aligned (4.52.1) ................................................................................. 80

45.2.4.11d.8 Lane 0 aligned (4.52.0) ................................................................................. 80

45.2.4.11e Multi-lane BASE-R PHY XS alignment status 4 register (Register 4.53) ............. 80

45.2.4.11e.1 Lane 15 aligned (4.53.7)............................................................................... 81

45.2.4.11e.2 Lane 14 aligned (4.53.6)............................................................................... 81

45.2.4.11e.3 Lane 13 aligned (4.53.5)............................................................................... 81

45.2.4.11e.4 Lane 12 aligned (4.53.4)............................................................................... 81

45.2.4.11e.5 Lane 11 aligned (4.53.3)............................................................................... 81

45.2.4.11e.6 Lane 10 aligned (4.53.2)............................................................................... 82

45.2.4.11e.7 Lane 9 aligned (4.53.1)................................................................................. 82

45.2.4.11e.8 Lane 8 aligned (4.53.0)................................................................................. 82

45.2.4.11f PHY XS lane mapping, lane 0 register (Register 4.400) ........................................ 82

45.2.4.11g PHY XS lane mapping, lane 1 through lane 15 registers (Registers 4.401

through 4.415)......................................................................................................... 82

45.2.4.11h PHY XS FEC symbol error counter lane 0 (Register 4.600, 4.601)....................... 82

45.2.4.11i PHY XS FEC symbol error counter lane 1 through 15 (Registers 4.602

through 4.631)......................................................................................................... 83

45.2.4.11j PHY XS FEC control register (Register 4.800)...................................................... 83

45.2.4.11j.1 PHY XS FEC degraded SER enable (4.800.2)............................................. 83

45.2.4.11j.2 PHY XS FEC bypass indication enable (4.800.1) ........................................ 83

45.2.4.11k PHY XS FEC status register (Register 4.801)........................................................ 84

45.2.4.11k.1 Remote degraded SER received (4.801.5).................................................... 84

45.2.4.11k.2 PHY XS FEC degraded SER (4.801.4) ........................................................ 84

45.2.4.11k.3 PHY XS FEC degraded SER ability (4.801.3) ............................................. 84

45.2.4.11k.4 PHY XS FEC high SER (4.801.2)................................................................ 85

45.2.4.11k.5 PHY XS FEC bypass indication ability (4.801.1) ........................................ 85

45.2.4.11l PHY XS FEC corrected codewords counter (Register 4.802, 4.803)..................... 85

45.2.4.11m PHY XS FEC uncorrected codewords counter (Register 4.

804, 4.805)................. 85

45.2.4.11n PHY XS FEC degraded SER activate threshold register (Register 4.806,

4.807) ...................................................................................................................... 86

45.2.4.11o PHY XS FEC degraded SER deactivate threshold register (Register 4.808,

4.809) ...................................................................................................................... 86

45.2.4.11p PHY XS FEC degraded SER interval register (Register 4.810, 4.811).................. 86

45.2.5 DTE XS registers .............................................................................................................. 87

45.2.5.1 DTE XS control 1 register (Register 5.0) ............................................................... 88

45.2.5.4 DTE XS speed ability (Register 5.4) ...................................................................... 88

45.2.5.4.a 400G capable (5.4.9)..................................................................................... 88

45.2.5.4.b 200G capable (5.4.8)..................................................................................... 89

45.2.5.11a BASE-R DTE XS status 1 register (Register 5.32) ................................................ 89

45.2.5.11a.1 BASE-R DTE XS receive link status (5.32.12)............................................ 89

45.2.5.11b BASE-R DTE XS test-pattern control register (Register 5.42) .............................. 89

45.2.5.11b.1 Transmit test-pattern enable (5.42.3)............................................................ 90

45.2.5.11c Multi-lane BASE-R DTE XS alignment status 1 register (Register 5.50) ............. 90

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45.2.5.11c.1 DTE XS lane alignment status (5.50.12) ...................................................... 90

45.2.5.11d Multi-lane BASE-R DTE XS alignment status 3 register (Register 5.52) ............. 90

45.2.5.11d.1 Lane 7 aligned (5.52.7) ................................................................................. 91

45.2.5.11d.2 Lane 6 aligned (5.52.6) ................................................................................. 91

45.2.5.11d.3 Lane 5 aligned (5.52.5) ................................................................................. 91

45.2.5.11d.4 Lane 4 aligned (5.52.4) ................................................................................. 91

45.2.5.11d.5 Lane 3 aligned (5.52.3) ................................................................................. 91

45.2.5.11d.6 Lane 2 aligned (5.52.2) ................................................................................. 92

45.2.5.11d.7 Lane 1 aligned (5.52.1) ................................................................................. 92

45.2.5.11d.8 Lane 0 aligned (5.52.0) ................................................................................. 92

45.2.5.11e Multi-lane BASE-R DTE XS alignment status 4 register (Register 5.53) ............. 92

45.2.5.11e.1 Lane 15 aligned (5.53.7)............................................................................... 93

45.2.5.11e.2 Lane 14 aligned (5.53.6)............................................................................... 93

45.2.5.11e.3 Lane 13 aligned (5.53.5)............................................................................... 93

45.2.5.11e.4 Lane 12 aligned (5.53.4)............................................................................... 93

45.2.5.11e.5 Lane 11 aligned (5.53.3)............................................................................... 93

45.2.5.11e.6 Lane 10 aligned (5.53.2)............................................................................... 93

45.2.5.11e.7 Lane 9 aligned (5.53.1)................................................................................. 93

45.2.5.11e.8 Lane 8 aligned (5.53.0)................................................................................. 93

45.2.5.11f DTE XS lane mapping, lane 0 register (Register 5.400) ........................................ 93

45.2.5.11g DTE XS lane mapping, lane 1 through lane 15 registers (Registers 5.401

through 5.415)......................................................................................................... 94

45.2.5.11h DTE XS FEC symbol error counter lane 0 (Register 5.600, 5.601) ....................... 94

45.2.5.11i DTE XS FEC symbol error counter lane 1 through 15 (Registers 5.602

through 5.631)......................................................................................................... 94

45.2.5.11j DTE XS FEC control register (Register 5.800)...................................................... 95

45.2.5.11j.1 DTE XS FEC degraded SER enable (5.800.2) ............................................. 95

45.2.5.11j.2 DTE XS FEC bypass indication enable (5.800.1) ........................................ 95

45.2.5.11k DTE XS FEC status register (Register 5.801) ........................................................ 95

45.2.5.11k.1 Local degraded SER received (5.801.6) ....................................................... 96

45.2.5.11k.2 Remote degraded SER received (5.801.5).................................................... 96

45.2.5.11k.3 DTE XS FEC degraded SER (5.801.4)......................................................... 96

45.2.5.11k.4 DTE XS FEC degraded SER ability (5.801.3) ............................................. 96

45.2.5.11k.5 DTE XS FEC high SER (5.801.2) ................................................................ 96

45.2.5.11k.6 DTE XS FEC bypass indication ability (5.801.1) ........................................ 97

45.2.5.11l DTE XS FEC corrected codewords counter (Register 5.802, 5.803) ..................... 97

45.2.5.11m DTE XS FEC uncorrected codewords counter (Register 5.804, 5.805) ................. 97

45.2.5.11n DTE XS FEC degraded SER activate threshold register (Register 5.806,

5.807) ...................................................................................................................... 97

45.2.5.11o DTE XS FEC degraded SER deactivate threshold register (Register 5.808,

5.809) ...................................................................................................................... 98

45.2.5.11p DTE XS FEC degraded SER interval register (Register 5.810, 5.811) .................. 98

78. Energy-Efficient Ethernet (EEE) .......................................................................................................... 99

78.1 Overview..................................................................................................................................... 99

78.1.4 PHY types optionally supporting EEE ............................................................................. 99

78.5 Communication link access latency.......................................................................................... 100

78.5.1 10 Gb/s PHY extension using extender sublayers XGXS .............................................. 100

90. Ethernet support for time synchronization protocols......................................................................... 101

90.1 Introduction............................................................................................................................... 101

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116. Introduction to 200 Gb/s and 400 Gb/s networks ............................................................................... 102

116.1 Overview................................................................................................................................... 102

116.1.1 Scope............................................................................................................................... 102

116.1.2 Relationship of 200 Gigabit and 400 Gigabit Ethernet to the ISO OSI reference

model .............................................................................................................................. 102

116.1.3 Nomenclature.................................................................................................................. 103

116.1.4 Physical Layer signaling systems ................................................................................... 104

116.2 Summary of 200 Gigabit and 400 Gigabit Ethernet sublayers ................................................. 105

116.2.1 Reconciliation Sublayer (RS) and Media Independent Interface ................................... 105

116.2.2 200GMII and 400GMII Extender Sublayers (200GXS and 400GXS)........................... 105

116.2.3 Physical Coding Sublayer (PCS) .................................................................................... 106

116.2.4 Physical Medium Attachment (PMA) sublayer.............................................................. 106

116.2.5 Physical Medium Dependent (PMD) sublayer ............................................................... 106

116.2.6 Management interface (MDIO/MDC) ............................................................................ 106

116.2.7 Management.................................................................................................................... 106

116.3 Service interface specification method and notation ................................................................ 106

116.3.1 Inter-sublayer service interface....................................................................................... 107

116.3.2 Instances of the Inter-sublayer service interface............................................................. 107

116.3.3 Semantics of inter-sublayer service interface primitives................................................ 107

116.3.3.1 IS_UNITDATA_i.request..................................................................................... 107

116.3.3.1.1 Semantics of the service primitive.............................................................. 108

116.3.3.1.2 When generated .......................................................................................... 109

116.3.3.1.3 Effect of receipt .......................................................................................... 109

116.3.3.2 IS_UNITDATA_i.indication ................................................................................ 110

116.3.3.2.1 Semantics of the service primitive.............................................................. 110

116.3.3.2.2 When generated .......................................................................................... 110

116.3.3.2.3 Effect of receipt .......................................................................................... 110

116.3.3.3 IS_SIGNAL.indication ......................................................................................... 110

116.3.3.3.1 Semantics of the service primitive.............................................................. 110

116.3.3.3.2 When generated .......................................................................................... 110

116.3.3.3.3 Effect of receipt .......................................................................................... 110

116.4 Delay constraints....................................................................................................................... 111

116.5 Skew constraints ....................................................................................................................... 112

116.6 FEC Degrade............................................................................................................................. 115

116.7 State diagrams........................................................................................................................... 116

116.8 Protocol implementation conformance statement (PICS) proforma......................................... 117

117. Reconciliation Sublayer (RS) and Media Independent Interface for 200 Gb/s and 400 Gb/s

operation (200GMII and 400GMII).................................................................................................... 118

117.1 Overview................................................................................................................................... 118

117.1.1 Summary of major concepts ........................................................................................... 119

117.1.2 Application...................................................................................................................... 119

117.1.3 Rate of operation............................................................................................................. 119

117.1.4 Delay constraints............................................................................................................. 119

117.1.5 Allocation of functions ................................................................................................... 120

117.1.6 200GMII/400GMII structure .......................................................................................... 120

117.1.7 Mapping of 200GMII/400GMII signals to PLS service primitives................................ 120

117.2 200GMII/400GMII data stream................................................................................................ 120

117.3 200GMII/400GMII functional specifications........................................................................... 120

117.4 LPI Assertion and Detection..................................................................................................... 120

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117.5 Protocol implementation conformance statement (PICS) proforma for Clause 117,

Reconciliation Sublayer (RS) and Media Independent Interface for 200 Gb/s and 400 Gb/s

operation (200GMII and 400GMII).......................................................................................... 121

117.5.1 Introduction..................................................................................................................... 121

117.5.2 Identification ................................................................................................................... 121

117.5.2.1 Implementation identification.............................................................................. 121

117.5.2.2 Protocol summary ................................................................................................. 121

117.5.3 Major capabilities/options............................................................................................... 122

117.5.4 PICS proforma tables for Reconciliation Sublayer (RS) and Media Independent

Interface for 200 Gb/s and 400 Gb/s operation (200GMII and 400GMII)..................... 122

117.5.4.1 General ................................................................................................................. 122

117.5.4.2 Mapping of PLS service primitives ...................................................................... 122

117.5.4.3 Data stream structure ............................................................................................ 123

117.5.4.4 200GMII/400GMII signal functional specifications ............................................ 123

117.5.4.5 Link fault signaling state diagram ....................................................................... 124

117.5.4.6 LPI functions......................................................................................................... 124

118. 200GMII Extender, 400GMII Extender, 200GMII Extender Sublayer (200GXS), and 400GMII

Extender Sublayer (400GXS) ............................................................................................................. 125

118.1 Overview................................................................................................................................... 125

118.1.1 Summary of major concepts ........................................................................................... 126

118.1.2 200GXS/400GXS Sublayer ............................................................................................ 126

118.1.3 200GAUI-n/400GAUI-n................................................................................................. 126

118.2 FEC Degrade............................................................................................................................. 126

118.2.1 DTE XS FEC Degrade signaling .................................................................................... 126

118.2.2 PHY XS FEC Degrade signaling.................................................................................... 127

118.3 200GXS and 400GXS partitioning example ............................................................................ 127

118.4 200GXS and 400GXS MDIO function mapping...................................................................... 127

118.5 Protocol implementation conformance statement (PICS) proforma for Clause 118,

200GMII Extender, 400GMII Extender, 200GMII Extender Sublayer (200GXS), and

400GMII Extender Sublayer (400GXS) ................................................................................... 131

118.5.1 Introduction..................................................................................................................... 131

118.5.2 Identification ................................................................................................................... 131

118.5.2.1 Implementation identification.............................................................................. 131

118.5.2.2 Protocol summary ................................................................................................. 131

118.5.3 Major capabilities/options............................................................................................... 132

118.5.4 PICS proforma tables for 200GMII Extender, 400GMII Extender, 200GMII

Extender Sublayer (200GXS), and 400GMII Extender Sublayer (400GXS)................. 132

118.5.4.1 Transmit function.................................................................................................. 132

118.5.4.2 Receive function ................................................................................................... 133

118.5.4.3 64B/66B coding rules ........................................................................................... 133

118.5.4.4 Scrambler and descrambler................................................................................... 134

118.5.4.5 Alignment markers ............................................................................................... 134

118.5.5 Test-pattern modes.......................................................................................................... 134

118.5.6 Bit order .......................................................................................................................... 134

118.5.7 Management.................................................................................................................... 135

118.5.7.1 State diagrams....................................................................................................... 135

118.5.7.2 Loopback ............................................................................................................. 135

118.5.7.3 Delay constraints................................................................................................... 136

119. Physical Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R ................... 137

119.1 Overview................................................................................................................................... 137

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119.1.1 Scope............................................................................................................................... 137

119.1.2 Relationship of 200GBASE-R and 400GBASE-R to other standards ........................... 137

119.1.3 Physical Coding Sublayer (PCS) .................................................................................... 137

119.1.4 Inter-sublayer interfaces ................................................................................................. 138

119.1.4.1 PCS service interface (200GMII/400GMII) ......................................................... 138

119.1.4.2 Physical Medium Attachment (PMA) service interface ....................................... 138

119.1.5 Functional block diagram ............................................................................................... 139

119.2 Physical Coding Sublayer (PCS) .............................................................................................. 140

119.2.1 Functions within the PCS ............................................................................................... 140

119.2.2 Use of blocks .................................................................................................................. 140

119.2.3 64B/66B code ................................................................................................................. 141

119.2.3.1 Notation conventions ............................................................................................ 141

119.2.3.2 64B/66B block structure ....................................................................................... 141

119.2.3.3 Control codes ........................................................................................................ 141

119.2.3.4 Valid and invalid blocks ....................................................................................... 142

119.2.3.5 Idle (/I/) ................................................................................................................. 142

119.2.3.6 Start (/S/)............................................................................................................... 142

119.2.3.7 Terminate (/T/)...................................................................................................... 142

119.2.3.8 Ordered set (/O/) ................................................................................................... 142

119.2.3.9 Error (/E/).............................................................................................................. 142

119.2.4 Transmit .......................................................................................................................... 142

119.2.4.1 Encode and rate matching..................................................................................... 142

119.2.4.2 64B/66B to 256B/257B transcoder....................................................................... 143

119.2.4.3 Scrambler .............................................................................................................. 145

119.2.4.4 Alignment marker mapping and insertion ............................................................ 145

119.2.4.4.1 AM creation for the 200GBASE-R PCS .................................................... 146

119.2.4.4.2 AM creation for the 400GBASE-R PCS .................................................... 148

119.2.4.5 Pre-FEC distribution ............................................................................................. 150

119.2.4.6 Reed-Solomon encoder......................................................................................... 150

119.2.4.7 Symbol distribution............................................................................................... 152

119.2.4.8 Transmit bit ordering and distribution .................................................................. 153

119.2.4.9 Test-pattern generators ......................................................................................... 155

119.2.5 Receive function ............................................................................................................. 155

119.2.5.1 Alignment lock and deskew.................................................................................. 155

119.2.5.2 Lane reorder and de-interleave ............................................................................. 155

119.2.5.3 Reed-Solomon decoder......................................................................................... 155

119.2.5.4 Post FEC interleave .............................................................................................. 156

119.2.5.5 Alignment marker removal................................................................................... 156

119.2.5.6 Descrambler .......................................................................................................... 156

119.2.5.7 256B/257B to 64B/66B transcoder....................................................................... 157

119.2.5.8 Decode and rate matching..................................................................................... 157

119.2.6 Detailed functions and state diagrams ............................................................................ 158

119.2.6.1 State diagram conventions .................................................................................... 158

119.2.6.2 State variables ......................................................................................................

. 158

119.2.6.2.1 Constants..................................................................................................... 158

119.2.6.2.2 Variables ..................................................................................................... 158

119.2.6.2.3 Functions..................................................................................................... 160

119.2.6.2.4 Counters ...................................................................................................... 162

119.2.6.3 State diagrams....................................................................................................... 162

119.3 PCS management...................................................................................................................... 167

119.3.1 PCS MDIO function mapping ........................................................................................ 167

119.4 Loopback .................................................................................................................................. 168

119.5 Delay constraints....................................................................................................................... 168

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