IEEE固态电路期刊特别版：欧洲固态电路会议论文集

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"JSSC_202007.pdf" 本期刊（IEEE Journal of Solid-State Circuits）旨在出版关于固态电路的论文，每月出版一卷，以晶体管级别的集成电路设计为重点。下面是本期刊的摘要信息：专题篇：45th IEEE European Solid-State Circuits Conference (ESSCIRC) 在本期刊的专题篇中， guest editor L.Breems、P.Reynaert 和 S.Clerc 介绍了第 45 届 IEEE 欧洲固态电路大会（ESSCIRC）的最新研究成果。论文摘要 1. 单芯片双向神经接口作者 J.P.Uehlin 等人提出了一个单芯片双向神经接口，具有高压刺激和自适应伪像取消功能，使用标准 CMOS 工艺实现。 2. 128x128 SPAD 运动触发式ToF 图像传感器作者 F.Mattioli Della Rocca 等人设计了一款 128x128 SPAD 运动触发式ToF 图像传感器，具有像素级直方图和列平行视觉处理器。 3. 1310/1550nm 光接收器作者 W.Diels 等人提出了一个使用 Schottky 光电二极管的 1310/1550nm 光接收器，实现了高速数据传输。 4. 低功率高选择性信道滤波器作者 B.J.Thijssen 等人设计了一款低功率高选择性信道滤波器，使用变压器-电容模拟 FIR 滤波器实现了高频率信号处理。 5. 64 通道发送波束形成器作者 A64-Channel Transmit Beamformer 等人提出了一个 64 通道发送波束形成器，具有 ±30V 双极性高压脉冲器，用于高频率数据传输。这些论文涵盖了固态电路设计的多个方面，包括神经接口、图像传感器、光接收器、信道滤波器和波束形成器等，展示了当前固态电路领域的最新研究成果和技术进展。

ELANSARY et al.: 50nW OPAMP-LESS  -MODULATE D BIOIMPEDANCE SPECTRUM ANALYZER 1975

Fig. 5. Opamp-less  -modulated ADC implementation: a conventional TIA integrator is replaced with a large capacitor as a passive integrator. The ADC

digital output is multiplied by a square wave using a simple

XOR gate.

higher frequencies and the quantization noise to be much lower

than Nyquist-rate ADCs at low frequencies (baseband). In the

proposed FRA scheme, the ADC output multibit multiplica-

tion by sinewave coefﬁcients [Fig. 4(c) and (e)] is replaced

with a single-bit squarewave multiplication [Fig. 4(d) and (f)].

Replacing the high-resolution sinewave by its 1-bit squarewave

representatio n causes additional spectral components due to

the harmonics of the squarewave as shown in Fig. 4(f).

Due to the nature of the square wave, where the weight of

its harmonics decreases hyperbolically with frequency, the

strong  high-frequency noise harmonics do not signiﬁcantly

corrupt the outp ut result of the multiply-and-accumulate oper-

ation, allowing the system to take advantage of the low-noise

baseband, leading to a higher sensitivity when compared with

conventional implementations. Hence, the real and imaginary

components of Z are efﬁciently computed by using a single-bit

square wave, and a 90

◦

-delayed version of it, instead of

sin(ω

t) and cos(ω

t) f unctions. This eliminates th e need

to store these functions in a large and power-consuming

SRAM. Even more importantly, this also eliminates the area

and energy requirements of a multibit multiplier and adder,

which are prohibitive for implantable applications. In this case,

the reuse of a single MAC operation using time multiplexer

becomes unnecessarily co mplicated in this scheme, as simulta-

neous extraction of the real and imaginary components comes

with using only a single

XOR gate and a counter.

IV. O

PAMP-LESS  ADC

The development of the biocompatible antifouling layer,

discussed in Section II, enables chronic implantation of the

proposed impedance spectrum analyzer. Chronic implantation

of biosensory devices is necessary for long-term studies, which

dictates speciﬁc requirements on the implanted device, such as

biocompatibility to avoid any tissue-implant reaction, small

form factor, high level of integration, and ultr alow power

consumption. While biocomatibility is taken care of by virtue

of the presented antifouling layer, low power consumption

and high integration level are ensured by the novel channel

architecture presented in this section.

For biochemical sensing, amperometry is required for mea-

suring ion concentrations. Typically, a transimpedance ampli-

ﬁer (TIA) is employed to provide a minimal input impedance

and to maintain the input node voltage level unchanged

during current sensing. For these two requirements, a negative

feedback loop is necessary to set the virtual ground at the

input node of the readout circuit while providing the required

low input impedance. Conventionally, an ampliﬁer (usually

an opamp/OTA) with a passive feedback network is used to

perform this function. To have the sufﬁcient gain and band-

width for maintaining the feedback, 30% to 50% of the readout

circuitry power budget is consumed in the ampliﬁer [4], [5],

[9], [16], whereas the rest of the power budget is divided

among ADC, digital signal processing, and biasing circuitry.

A major power reduction can be achieved if the negative

feedback is maintained without the use of an ampliﬁer.

In the case of a delta-sigma ADC, an integrator is included

in the negative feedback loop to accumulate the  loop

error and to produce an output bit stream that resembles

the analog input after decimation. In the presented channel,

we eliminate the opamp and replace the loop integrator by a

large capacitance C

INT

,inthewaydepictedinFig.5.This

opamp-less  negative feedback loop is used to maintain

a low input impedance and to set the virtual voltage at the

input node. The difference between the feedback and the input

currents is integrated on C

INT

, while the voltage at C

INT

which is also the input node, is set by the loop comparator

reference voltage V

REF

(Fig. 5). Since a capacitor has a very

high impedance at low frequencies, the feedback loop gain

is preserved for low-frequency input signals, which is well

suited for biomedical applications. Provided that the loop is

fast enough to track the voltage variations at the input node

(on C

INT

) caused by fast or relatively large input currents,

the operation of the loop is maintained and the input node

issetatV

REF

. This is achieved by choosing high sampling

frequency when compared with the input frequency as well as

other conditions that are detailed in Section IV-B.

In addition, as indicated in Sectio n III, the  output stream

allows to perform the MAC operation inside the ADC itself

by replacing the multibit sin/cos multip lication with area- and

power-efﬁcient single-b it squarewave multiplication [Fig. 4(b),

(d) and (f)].

A. Passive Integrators

As mentioned earlier in this section, a fundamental building

block in  ADCs is the integrator (or the loop ﬁlter),

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1976 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL . 55, NO. 7, JULY 2020

Fig. 6. First-order  -modulated ADC operation phases. ADC feedback loop

maintains the current input node as a virtual ground. (a) Loop compensates

input currents by pushing/pulling charge from the input passive integration

capacitor according to comparator decision. (b) Clock edges at which the

charge pushing/pulling occurs.

as it performs the function of  loop error accumulation.

Conventionally, for continuous-time  loops, integrators are

implemented as active ﬁlters, using RC sections and opamps,

or g

-cells (G

-C circuits). In discrete-time  converters,

the loop ﬁlter is implemented using switched capacitor inte-

grators, which use OTAs for charge integration. In both cases

(opamps and G

-C circuits), high linearity is an important

design speciﬁcation that has to be maintained. In CMOS tech-

nologies, the realization o f highly-linear power-efﬁcient active

ﬁlters or switched capacitor integrators is getting more and

more challenging with short channel transistors. On the other

hand, the performance of digital building blocks and switches

is improving. It bodes well for over sampling ADCs, 

in our case, to employ passive switched-capacitor ﬁlters and

integrators, where the MOS transistor is only used as a switch.

A switch works better at higher frequencies as compared

with active ﬁlters and G

-C circuits, where the maximum

operating frequency is limited by the opamp settling. Also,

the input-referred noise of a passive switched-capacitor ﬁlter

is expected to be lower as it only employs one input capacitor.

It also exhibits higher linearity due to passive operation [17].

B. First-Order Opamp-Less  ADC

Fig. 6 illustrates the operation phases of the implemented

opamp-less channel. A charge-sharing DAC pushes/pulls

charge through a small capacitor C

DAC

to/from the much

larger integrator input capacitor C

INT

, depending on the com-

parator output. A high OSR is selected so that the digital

feedback loop maintains V

INT

approximately equal to V

REF

Fig. 7.  ADC comparator implementation. 100 k degeneration resistors

are used to further reduce the effect of hysteresis and path dependence on the

performance. Low-duty-cycle sample (clk 1) and decision (clk2) clocks are

used for power saving.

The OSR has to be high enough to keep the change in V

INT

with respect to the reference voltage V

REF

smaller than the

voltage change caused by the smallest desired input current

in,min

×T

INT

). The input current is integrated directly by

the input capacitor C

INT

leading to a voltage range smaller

than that on the conventional opamp feedback capacitor, but

this does not increase susceptibility to comparator noise. This

is because the opamp-less ADC rejects dc offset and 1/f noise

because, as proven later in this section, its transfer function is

approximately equivalent to that of an active-integrator 

ADC. Hence, inputs to the  loop before the integrator

will experience a low-pass signal-transfer function (STF).

For inputs that enter the loop after the integrator, they will

experience a high-pass signal-transfer function sim ilar to the

quantization noise-transfer function (NTF). Since the compara-

tor noise is generated in the loop after the integrator, it is

modulated to high frequencies together with the quantizatio n

noise [18].

The comparator circuit is depicted in Fig. 7. It consists of

a regenerative latch circuit with 90 k drain resistors and

input sampling transistors with 100 k degeneration resis-

tors. The values of these resistors were selected to minimize

power consumption at sampling and regeneration instants

while maintaining adequate accuracy and speed. Resistive

degeneration mitigates path dependence and hysteresis. The

dynamic/transient power consumption ( P

) of the comparator

is proportional to V

( P

 f

· V

· C). It is greatly

reduced by operating at low supply level of 0.6 V. The static

power consumption, due to the direct-path current, (P

)is

mainly caused by direct currents between the supply and the

ground during input sampling and decision phases. Therefore,

the width of the sampling pulse (CLK1) and decision pulse

(CLK2) are minimized (8 and 3 ns, respectively) and the drain

and degeneration resistors are increased and optimized to help

reduce the direct current path power dissipation.

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ELANSARY et al.: 50nW OPAMP-LESS  -MODULATE D BIOIMPEDANCE SPECTRUM ANALYZER 1977

Fig. 8. (a) Low-frequency input signal is dissected into inﬁnitesimal pulses

using FEM approximation. Input signal is approximated into a dc signal U

and small pulses U

. (b) and (c) compare the responses of conventional

acti ve integrator circuits, in (b), and the presented passive integrator circuit,

in (c), to the two input signal components.

To demonstrate the effect of using a passive integra-

tor, as compared with using an active integrator, on the

system-transfer function, a simpliﬁed analysis is done on both

active and passive integrators as shown in Fig. 8. Since the

bandwidth of the input signal is very low when compared

with the sampling frequency of the oversampled  ADC,

the problem is analyzed using ﬁnite element method (FEM),

as shown in Fig. 8(a). The input signal is divided into

small inﬁnitesimal samples with T

widths. Based on this

assumption, the input signal at each sample n consists of two

components: a dc component U

and a step function U

For an active integrator shown in Fig. 8(b), the two input

components affect the integrato r output in different manners.

The dc component U

charges the integrator capacitance C

INT

through the resistor R

, whereas the step function U

charges

INT

through the capacitor C

. The output voltage of the

integrator V

INT

at the end of each sample is represented by the

following equation, ignoring the minus sign of the inverting

ampliﬁer conﬁguration:

INT,n

= V

INT,n−1

INT

+ U

INT

= V

INT,n−1

+ αU

+ βU

(1)

where α is the ratio between the sampling time T

and the

circuit time constant R

INT

;andβ is the ratio between C

and the integration capacitance C

INT

. Fig. 8(c) shows the same

analysis applied on the passive integrator, resulting in the

following equation:

INT

= V

INT

n−1

· e

−

INT



1 −e

−

INT



+U

+ C

INT

.(2)

Fig. 9. Canonical form of ﬁrst-order  ADC. Conventional  ADC

branches are black and branches added as a result of using the passive

integrator are marked in red. The red branches can be ignored for α, β,

and γ all  1.

By increasing C

INT

to be large enough to satisfy the require-

ment of proper integ ration (much larger than C

), and reducing

to be much smaller than the time constant R

INT

, (2) can

be reduced to the following equation:

INT

= V

INT

n−1

− V

INT

n−1

INT

+ U

INT

+U

INT



1 −

INT



INT

= V

INT,n−1

+ αU

+ βU

− αV

INT,n−1

−β

U

. (3)

As derived in (3), the use of a passive integrator introduced

two new terms when compared with (1) of an active integrator

which are αV

INT,n−1

and β

U

Fig. 9 shows the superimposed z-domain models of both

the conventional active integrator (black) and the presented

 ADC (black and red). As discussed, removing the opamp

causes two additional branches with the weights α and β

appear. The absence of a TIA causes the 1-bit DAC to have

an additional unwanted branch connecting it to the comparator

input. The two designs become approximately equivalent when

the coefﬁcients α, β,andγ are all  1. This is true when:

1) the sam pling period is negligible when compared with

the time constant of the tissue-electrode interface; 2) C

INT

is much greater than the equivalent shunt capacitance of the

microelectrode; and 3) the input current is much smaller than

the full-scale input current of the ADC. In the context of in

vivo potassium amperometry, condition (1) is satisﬁed when

the ADC operates at sampling frequencies in the megahertz

range (above 800 kHz) for the input bandwidth of a few

kilohertz (5 kHz). Condition (2) is met by keeping size of

the WE small (50 μm ×100 μm). C

INT

is the MIM

capacitor which shields the WE from underneath, thus the

WE capacitance is effectively equal to the fringe capacitance

between the WE and the adjacent reference electrode.

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1978 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL . 55, NO. 7, JULY 2020

Fig. 10. Experimentally measured and simulated characterization of the

opamp-less  ADC SNDR. (a) FFT spectrum of the  output stream,

(b) SNDR plots versus inputs current leve ls at two different clock frequencies,

and (c) SNDR versus OSR.

It has to be noted that although the elimination of the opamp

from the system has reduced the power consumption severely

when compared with other systems, it also comes with some

drawbacks that had to be very carefully mitigated by accurately

selecting proper design choices of sampling frequency, elec-

trode sizes, suitable input range, and measuring environment.

These drawbacks, such as lack of linearity at high input fre-

quencies and amplitudes, are mitigated by incr easing the OSR.

Due to the nature of the feedback single-bit DAC, increasing

the OSR leads to increasing the rate of charge sharing at

the integrator capacitor w hich in turn leads to increasing the

feedback loop gain. Hence, for higher frequencies, the same

linearity an d SNR levels as the opamp-based designs are

achieved at the expense of high dynamic power. Susceptibility

to large artifacts is also overcome. Since the ADC architec-

ture is continuous-time  , intrinsic anti-aliasing ﬁlter and

low-pass ﬁlter-transfer functions are incorporated. In case of

high-frequency artifacts, they will be ﬁltered out by these

ﬁlters. If they are at low frequencies and have large amplitudes

enough to saturate the passive  ADC input circuit, they will

saturate any opamp-based circuit as well. Various precautions

have been made to ensure proper measurement results, such

as electrodes size o ptimization, shielding, and encapsulation

of the IC.

V. E

XPERIMENTAL RESULTS

Fig. 10(a) shows the FFT spectrum of the output  ADC

stream. The channel achieves an signal-to-noise-and-distortion

ratio (SNDR) of 50.3 dB at 1 MHz sampling frequency over

Fig. 11. Experimentally measured characterization of the opamp-less 

ADC. (a) ADC Digital output versus input current levels. (b) Impedance

calculation errors compared to a 10-bit multiplying ADC output.

5 kHz bandwidth. Fig. 10(b) shows the SNDR plot of the ADC

at two sampling frequencies: 846 ksps and 8.46 Msps. The

latter yields a higher dynamic range, due to an increased range

of currents that can be pushed/pulled by the DAC. Fig. 10(c)

shows that the OSR improves the SNDR by ∼28 dB/decade.

Fig. 11(a) depicts the ADC output versus the input current at

the two sampling frequencies. The experimental results differ

from the simulated results for small currents as this is near

the 1 pA sensitivity. Fig. 11(b) shows the error in the digital

impedance output using both a 10-bit sine wave and its 1-bit

(square wave) approximation. For OSR of 500 or more, the

computation error is less than 2%.

The IC was validated in vivo in an anesthetized immobilized

mouse. The IC was mounted on a ﬂexible polyimide electrode

array shown in Fig. 12, with its four sensory gold strips

chemically functionalized as shown in Fig. 2. The chip pads

are wire bonded to the solderin g pads of the microelectrode

array. The IC is, then, covered by epoxy. The remaining area

of the solder pads, not covered with epoxy, is used to connect

the chip signals to the benchtop instruments. This sensor array

was then placed on a section of the cerebral cortex of a mouse

exposed by craniotomy.

Fig. 13 depicts experimentally measured calibration curve

for both [K

]and[Na

]. As shown, the responses of the

antifouling microelectrodes to sodium and potassium ions are

distinguishable. These curves are obtained by varying the

concentrations of K

and Na

in an artiﬁcial CSF solution.

The electrode pad capacitance (C

) is measured using the same

impedance extraction architecture described in Section III.

The potassium and sodium concentrations are increased

equally as depicted in Fig. 13 (a) (2.5, 4.5, 6.5, and 10 mM).

At each concentration level, an interrogation voltage of

8mV

p-p

is swept across frequencies from 100 Hz to 1 kHz

on the solution [Fig. 14(a)]. The current output is recorded

using the ADC [Fig. 14(b)]. As seen in Fig. 14(b), the current

magnitude increases when interrogation frequency increases

as the capacitance impedance reduces [1/(jωC

)], while the

phase of the current signal has a 90

◦

-phase shift with the

voltage signal. The capacitance of the microelectrode pads

) changes much more for changes in [Na

] than for [K

]

changes. The concentration range of potassium from 2 to

10 mM has been measured by the presented EIS channel that

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ELANSARY et al.: 50nW OPAMP-LESS  -MODULATE D BIOIMPEDANCE SPECTRUM ANALYZER 1979

Fig. 12. (a) Four-channel gold microelectrode array implemented on a

polyimide substrate (four out of the six contacts are used). (b) Connection

between the IC and the polyimide ﬂexible electrode.

Fig. 13. Potassium and sodium concentrations calibration curves. (a) Elec-

trode pad capacitance (C

)versustimeand(b)C

versus concentration. C

changes much more for changes in [Na

]than[K

] changes.

has a dynamic range of 1 pA–20 nA with a bandwidth of

5 kHz. This range includes the typical range of these ions

concentration in a nonpathological brain.

A block diagram of the in vivo experimental setup is

shown in Fig. 15(a). The mouse brain cortex is subjected to

optogenetic stimulation pulses [14]. The impedance analyzer

IC is mounted on the polyimide ﬂexible substrate [Figs. 12(b)

and 15(b)]. The outputs from the four-channel microelectrode

and the reference glass electrode are stored in an off-chip

memory for display and comparison.

Fig. 16 shows [K

] concentration measured in vivo in

an anesthetized mouse during pulsed optogenetic stimula-

tion (under an ethics p rotocol at Toronto Western Hospital).

In Fig. 16(a), the [K

] variation recorded by a double-barrel

glass electrode inserted in the cortex layer 2–3, serving as a

control signal for comparison, is shown.

Fig. 16(b) depicts the impedance of the gold microelec-

trode placed on the brain cortex, recorded by the  ADC

simultaneously with the control signal. To record real-time

] variation by gold microelectrodes, an 8 mV peak-to-

peak sinusoidal voltage generated off-chip is swept across

Fig. 14. Frequency sweep for impedance spectroscopy. (a) Interrogation

voltage signal frequency sweep from 20 Hz to 5 kHz. (b) Output current

from ADC after decimation and ﬁltering.

Fig. 15. In vivo measurement setup. (a) Block diagram of in vivo channel

measurement setup and instruments. (b) Measurement setup of the experiment

done on an anesthetized mouse. Optogenetic stimulation pulses are applied

to the brain cortex. A twisted pair wires are used to connect the IC to the

off-chip instruments to minimize interference.

frequencies, from 100 Hz to 1 kHz. The resulting current is

recorded by the  ADC and processed by a reconstruction

algorithm that extracts the R and C parameters of the series

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