5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR3
SO-DIMM A
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
EVT Check
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
DDR_A
_D31
DDR_A
_D12
DDR_CK
E0_DIMMA
DDR_A
_D59
DDR_A
_D6
DDR_A
_MA3
DDR_
CS
1_DIMMA#
DDR_A
_D39
DDR_A
_BS1
DDR_A
_DQS0
DDR_A
_WE#
DDR_A
_MA7
DDR_A
_MA0
DDR_A
_DM2
DDR_A
_DM1
DDR_A
_DQS7
DDR_A
_D0
DDR_A
_D57
DDR_A
_D46
DDR_A_D28
DDR_A
_DM0
DDR_A
_D19
DDR_A
_DQS#5
DDR_A
_D51
DDR_A
_D4
DDR_A
_DM4
DDR_A_D30
DDR_A
_DQS2
DDR_A
_D44
DDR_A
_RAS#
DDR_A
_D33
DDR_A
_D58
DDR_A
_DM5
DDR_A
_DQS3
DDR_A
_MA8
DDR_CS
0_DIMMA#
DDR_A
_D10
DDR_A
_MA6
DDR_A
_D27
DDR_A_D3
DDR3_
DRAMRST#
DDR_A
_MA10
DDR_A
_DQS#7
DDR_A
_D1
DDR_A
_DQS#6
DDR_A
_D40
DDR_A
_MA9
DDR_A_D16
DDR_A
_D29
DDR_A
_DQS#4
DDR_A
_D52
DDR_A
_DM3
DDR_A
_DQS5
DDR_A
_D54
DDR_A
_D49
DDR_A
_BS2
DDR_A
_D45
DDR_A
_D9
DDR_A
_DM7
DDR_A_D7
DDR_A
_MA1
DDR_A
_D13
DDR_A_D20
DDR_A
_D60
DDR_A
_BS0
DDR_A
_CAS#
M_O
DT0
DDR_A
_D37
DDR_A
_MA5
DDR_A
_DQS#1
DDR_A
_MA14
DDR_A_D55
DDR_A
_MA4
DDR_A
_D21
DDR_A
_D62
DDR_A
_D24
DDR_A_D15
DDR_A
_D23
DDR_A
_D56
DDR_A
_D53
DDR_A
_D47
DDR_A
_D18
M_O
DT1
DDR_A
_D43
DDR_A
_D34
M_C
LK_DDR1
M_C
LK_DDR#1
DDR_A
_D48
DDR_A
_DQS#2
DDR_A_D11
DDR_A
_D38
M_C
LK_DDR0
M_C
LK_DDR#0
DDR_A_DQS#3
DDR_A
_D32
DDR_A
_D8
DDR_A
_DQS1
DDR_A
_MA13
DDR_A
_MA11
DDR_A_D50
DDR_A
_D61
DDR_A
_MA2
DDR_A
_D41
DDR_A
_D17
DDR_A
_D36
DDR_A_D26
DDR_A
_D63
DDR_A
_D2
DDR_A
_D5
DDR_A
_D22
DDR_A
_D25
DDR_A
_DQS6
DDR_A
_D35
DDR_A
_D14
DDR_A
_MA12
DDR_A
_DQS#0
DDR_
A
_DQS4
DDR_A
_DM6
DDR_A
_D42
DDR_CK
E1_DIMMA
+VR
EF_DQ_DIMMA
+V
R
EF_CA
DDR_A_MA15
DDR_A
_DM0
DDR_A
_DM1
DDR_A
_DM2
DDR_A
_DM3
DDR_A
_DM4
DDR_A
_DM5
DDR_A
_DM6
DDR_A
_DM7
SMB_
CLK_S3
SMB_
DATA_S3
+VR
EF_CA
+VR
EF_DQ_DIMMA
DDR_A
_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A
_DQS[0..7]<7>
DDR_A_MA[0..15]<7>
DDR_CK
E0_DIMMA<7>
DDR_A
_BS2<7>
M_
C
LK_DDR0<7>
M_C
LK_DDR#0<7>
DDR_A
_BS0<7>
DDR_A
_WE#<7>
DDR_A
_CAS#<7>
DDR_CS
1_DIMMA#<7>
DDR_CK
E1_DIMMA <7>
DDR_A
_BS1 <7>
DDR_A
_RAS# <7>
DDR_CS
0_DIMMA# <7>
M_O
DT0 <7>
M_C
LK_DDR1 <7>
M_C
LK_DDR#1 <7>
M_O
DT1 <7>
DDR3_
DRAMRST# <13,6>
SMB_
CLK_S3 <13,17,37>
SMB_
DATA_S3 <13,17,37>
+VR
EF_CA <13>
+0.6
75VS
+3V
S
+1.35V +1.35V
+1.3
5V
+0.6
75VS
+VR
EF_CA_R
+1.3
5V
+VR
EF_DQ_DIMMA_R
+VR
EF_DQ_DIMMB
+VREF_DQ_DIMMA
+1.3
5V
+VR
EF_DQ_DIMMA
Title
Size Document Number Rev
Date: Sheet
of
Sec
urity Classification
Com
pal Secret Data
THI
S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Iss
ued Date
Deciphered Date
0.3
DDRI
II-SODIMM SLOT1
Cus
tom
12 61Wednesday, March 06, 2013
2011/06/
15 2012/07/11
Com
pal Electronics, Inc.
LA-
7981P
Tit
le
Size Document Number Rev
Date: Sheet
of
Sec
urity Classification
Com
pal Secret Data
THI
S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Iss
ued Date
Deciphered Date
0.3
DDRI
II-SODIMM SLOT1
Cus
tom
12 61Wednesday, March 06, 2013
2011/06/
15 2012/07/11
Com
pal Electronics, Inc.
LA-
7981P
Tit
le
Size Document Number Rev
Date: Sheet
of
Sec
urity Classification
Com
pal Secret Data
THI
S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Iss
ued Date
Deciphered Date
0.3
DDRI
II-SODIMM SLOT1
Cus
tom
12 61Wednesday, March 06, 2013
2011/06/
15 2012/07/11
Com
pal Electronics, Inc.
LA-
7981P
C65
2.
2U_0603_6.3V4Z
@
C65
2.
2U_0603_6.3V4Z
@
1
2
C68
2.
2U_0603_6.3V4Z
@
C68
2.
2U_0603_6.3V4Z
@
1
2
R40
1K
_0402_1%
R40
1K
_0402_1%
12
C79
0.
1U_0402_16V7K
C79
0.
1U_0402_16V7K
1
2
RP1
8
1K_0804_8P4R_1%
RP1
8
1K_0804_8P4R_1%
18
27
36
45
+
C8
1
220U
_6.3V_M
@
+
C8
1
220U
_6.3V_M
@
1
2
R45
24.9_0402_1%
@
R45
24.9_0402_1%
@
12
C70
10U_0603_6.3V6M
@
C70
10U_0603_6.3V6M
@
1
2
C67
0.
1U_0402_16V7K
C67
0.
1U_0402_16V7K
1
2
JDI
MM1
FOX_AS0A626-U8SN-7F
ME@
JDI
MM1
FOX_AS0A626-U8SN-7F
ME@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS
#0
10
DM0
11
DQS
0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ1
2
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS
#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ1
0
33
DQ1
4
34
DQ1
1
35
DQ1
5
36
VSS13
37
VSS14
38
DQ1
6
39
DQ2
0
40
DQ1
7
41
DQ2
1
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS
2
47
VSS17
48
VSS18
49
DQ2
2
50
DQ18
51
DQ23
52
DQ1
9
53
VSS19
54
VSS20
55
DQ2
8
56
DQ24
57
DQ29
58
DQ2
5
59
VSS21
60
VSS22
61
DQS
#3
62
DM3
63
DQS
3
64
VSS23
65
VSS24
66
DQ2
6
67
DQ3
0
68
DQ2
7
69
DQ3
1
70
VSS25
71
VSS26
72
A12
/BC#
83
A11
84
A9
85
A7
86
VDD
5
87
VDD
6
88
A8
89
A6
90
CKE
0
73
CKE
1
74
VDD
1
75
VDD
2
76
NC1
77
A15
78
BA2
79
A14
80
VDD
3
81
VDD
4
82
A5
91
A4
92
VDD
7
93
VDD
8
94
A3
95
A2
96
A1
97
A0
98
VDD
9
99
VDD
10
100
CK0
101
CK1
102
CK0
#
103
CK1
#
104
VDD
11
105
VDD
12
106
A10
/AP
107
BA1
108
BA0
109
RAS
#
110
VDD
13
111
VDD
14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD
15
117
VDD
16
118
A13
119
ODT
1
120
S1#
121
NC2
122
VDD
17
123
VDD
18
124
NCTE
ST
125
VREF
_CA
126
VSS27
127
VSS28
128
DQ3
2
129
DQ3
6
130
DQ3
3
131
DQ3
7
132
VSS29
133
VSS30
134
DQS
#4
135
DM4
136
DQS
4
137
VSS31
138
VSS32
139
DQ3
8
140
DQ3
4
141
DQ3
9
142
DQ3
5
143
VSS33
144
VSS34
145
DQ4
4
146
DQ4
0
147
DQ4
5
148
DQ4
1
149
VSS35
150
VSS36
151
DQS
#5
152
DM5
153
DQS
5
154
VSS37
155
VSS38
156
DQ4
2
157
DQ4
6
158
DQ4
3
159
DQ4
7
160
VSS39
161
VSS40
162
DQ
4
8
163
DQ
5
2
164
DQ4
9
165
DQ5
3
166
VSS41
167
VSS42
168
DQS
#6
169
DM6
170
DQS
6
171
VSS43
172
VSS44
173
DQ5
4
174
DQ
5
0
175
DQ
5
5
176
DQ5
1
177
VSS45
178
VSS4
6
179
DQ
6
0
180
DQ5
6
181
DQ6
1
182
DQ5
7
183
VSS47
184
VSS48
185
DQS
#7
186
DM7
187
DQS
7
188
VSS49
189
VSS50
190
DQ5
8
191
DQ6
2
192
DQ5
9
193
DQ6
3
194
VSS51
195
VSS52
196
SA0
197
EVENT
#
198
VDD
SPD
199
SDA
200
SA1
201
SCL
202
VTT
1
203
VTT
2
204
G1
205
G2
206
C72
10U
_0603_6.3V6M
C72
10U
_0603_6.3V6M
1
2
C86
2.
2U_0603_6.3V4Z
@
C86
2.
2U_0603_6.3V4Z
@
1
2
R472_0402_5% R472_0402_5%
12
C76
10U
_0603_6.3V6M
C76
10U
_0603_6.3V6M
1
2
C87
0.
1U_0402_16V7K
C87
0.
1U_0402_16V7K
1
2
C37
0.
022U_0402_16V7K
@
C37
0.
022U_0402_16V7K
@
1
2
C73
10U
_0603_6.3V6M
C73
10U
_0603_6.3V6M
1
2
C82
1U
_0402_6.3V6K
C82
1U
_0402_6.3V6K
1
2
C71
10U
_0603_6.3V6M
C71
10U
_0603_6.3V6M
1
2
C77
0.
1U_0402_16V7K
C77
0.
1U_0402_16V7K
1
2
C85
1U
_0402_6.3V6K
@
C85
1U
_0402_6.3V6K
@
1
2
C75
10U_0603_6.3V6M
C75
10U_0603_6.3V6M
1
2
C39
0.
022U_0402_16V7K
@
C39
0.
022U_0402_16V7K
@
1
2
C84
1U
_0402_6.3V6K
C84
1U
_0402_6.3V6K
1
2
R54
24.
9_0402_1%
@
R54
24.
9_0402_1%
@
12
C80
0.
1U_0402_16V7K
C80
0.
1U_0402_16V7K
1
2
C83
1U
_0402_6.3V6K
@
C83
1U
_0402_6.3V6K
@
1
2
C78
0.
1U_0402_16V7K
C78
0.
1U_0402_16V7K
1
2
C6
6
0.
1U_0402_16V7K
C6
6
0.
1U_0402_16V7K
1
2
C74
10U
_0603_6.3V6M
C74
10U
_0603_6.3V6M
1
2
R48 2
_0402_5%
R48 2
_0402_5%
1 2
C69
10U
_0603_6.3V6M
@
C69
10U
_0603_6.3V6M
@
1
2
R44
1K
_0402_1%
R44
1K
_0402_1%
12