FPGA架构概览与挑战

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“FPGA-survey资源 - FPGA基础学习资料，包含FPGA架构的调查与挑战” FPGA（Field-Programmable Gate Array）是可编程逻辑器件，它在过去十年间已成为数字电路实现的重要媒介。FPGA的核心在于其架构，这决定了它的可编程逻辑功能和互连方式。FPGA架构对最终设备的速度性能、面积效率和功耗有着显著的影响。这篇名为《FPGA架构：调查与挑战》的文章来自《电子设计自动化基础与趋势》杂志，由Ian Kuon、Russell Tessier和Jonathan Rose撰写。文章首先回顾了可编程逻辑器件的历史发展，这一部分可能会涵盖早期的PLD（Programmable Logic Device）到现代复杂FPGA的演变过程，包括它们在不同领域的应用和影响力。接着，文章深入探讨了构成FPGA可编程性的基础编程技术。这可能包括查找表（LUT）、配置存储器（Configuration Memory）、可编程逻辑块（CLB）、I/O单元（IOB）等核心组件的工作原理，以及它们如何通过硬件描述语言（如VHDL或Verilog）进行编程和设计。文章进一步详细描述了FPGA的架构设计。这部分可能会涉及路由资源（Routing Resources），如全局布线网络（Global Routing Networks）和局部布线资源（Local Routing Resources），它们对于确保信号在FPGA内部的快速、高效传输至关重要。此外，可能还会讨论时钟管理和同步问题，因为这直接影响到FPGA的性能和时序约束。作者们还可能分析了FPGA在速度、面积和功耗三者之间的权衡。这涉及到优化设计，如部分重配置（Partial Reconfiguration）技术，它允许FPGA在运行时改变部分逻辑，以适应不同的任务需求，同时减少功耗和提高效率。最后，文章讨论了FPGA面临的挑战，这可能包括不断提高的集成度带来的设计复杂性、功耗控制、以及与ASIC（Application-Specific Integrated Circuit）的竞争。此外，随着量子计算和高速通信等领域的进展，FPGA在新技术中的角色和未来发展趋势也是关注的重点。这篇资源适合于希望了解FPGA基本概念、设计原理和最新研究动态的学习者，无论是初学者还是有经验的工程师，都能从中获得宝贵的见解。通过深入理解FPGA的架构和编程技术，读者能够更好地设计和优化基于FPGA的系统，以满足不断变化的应用需求。

150 Programming Technologies

alternative technologies, in-system programming is not possible with

these devices. Instead, special programmers must be used to program

a device before it is mounted on a ﬁnal product. Finally, the one-time

programmability of anti-fuses makes it impossible for manufacturing

tests to detect all possible faults. Some faults will only be uncovered

after programming and, therefore, the yield after programming will be

less than the 100% yield of SRAM or ﬂoating-gate devices. Some cur-

rent devices are only expected to be programmed successfully with 90%

conﬁdence [2].

3.4 Summary

While the three programming technologies reviewed in this section

are used in modern devices, SRAM-based programming technology

has become the most widely used. Table 3.1 summarizes the dif-

ferences between the diﬀerent programming technologies. An ideal

technology would be non-volatile and reprogrammable using a stan-

dard CMOS process and oﬀer low on resistances and low para-

sitic capacitances. Clearly, none of the technologies satisﬁes all these

requirements. One of the primary reasons SRAM technology has

dominated is its use of standard CMOS manufacturing processes. For

this same reason, the dominance of SRAM-based programming tech-

nology can be expected to continue for the foreseeable future of CMOS

technology.

Table 3.1 Programming technology properties summary.

SRAM Flash Anti-fuse

Volatile? Yes No No

Reprogrammable? Yes Yes No

Area (storage High Moderate Low

element size) (6 transistors) (1 transistor) (0 transistors)

Manufacturing Standard Flash Anti-fuse

process? CMOS Process needs special

development

In-system

Yes Yes No

programmable?

Switch resistance ∼500–1000 Ω ∼500–1000 Ω 20–100 Ω

Switch capacitance ∼1–2 fF ∼1–2 fF <1fF

Programming yield 100% 100% > 90%

152 Logic Block Architecture

in the original gate arrays, the most simple and un-speciﬁc way of

providing this capability is to use a transistor as the basic logic ele-

ment, and build gates and storage elements from it. This approach was

indeed attempted in a commercial FPGA from the now-defunct com-

pany Crosspoint [144]. This kind of very ﬁne-grained logic block, how-

ever, requires the use of large amounts of programmable interconnect

to create any typical logic function. It will result in an FPGA that is

bound to suﬀer from area-ineﬃciency (because programmable routing

is expensive in terms of area), low performance (each routing “hop” is

slow), and high power consumption (because of the higher capacitance

of programmable interconnect that must be charged and discharged).

At the other extreme, a logic block could be an entire processor.

This approach exists in the commercial space, although processors are

mixed with some more ﬁne grained logic blocks in a device [13, 188,

189, 195, 196, 228, 231, 235]. Such a logic block on its own would not

have the performance gains that come from customizable hardware. In

addition, if such a block was used to implement a 2-input AND gate,

it would be incredibly ineﬃcient, which illustrates the danger of using

logic blocks that are too coarse-grained.

In between these extremes is a spectrum of logic block choices rang-

ing from ﬁne to coarse-grain logic blocks. FPGA architects over the last

two decades have selected basic logic blocks made of transistors (noted

above) [144], NAND gates [160], an interconnection of multiplexers [79],

lookup tables [49], and PAL-style wide-input gates [217]. These choices

were originally driven by intuitive insights on the part of architects,

typically with very little data or analysis, with a few exceptions [79].

In this survey, we discuss how the research foundations for choosing a

logic block were established, and then focus on the eﬀect of logic block

functionality on the three key metrics: area, speed, and power. In this

discussion, we use silicon area as the proxy for cost, as is common. For

a more detailed survey on the speciﬁcs of the logic blocks mentioned

above, see [167] or [43].

In addition to a basic logic block, many modern FPGAs contain a

heterogeneous mixture of diﬀerent blocks, some of which can only be

used for very speciﬁc functions, such as dedicated memory blocks or

multipliers. These structures are very eﬃcient at implementing speciﬁc

154 Logic Block Architecture

architectures to determine the eﬀect of processor architecture on per-

formance. The only alternative to this kind of empirical approach is

the use of a theoretical approach in which applications are modeled in

a statistical/graph-theoretical way, and the mapping of an application

onto an architecture is modeled through a probabilistic calculation or

through other theoretical machinery. While there have been a num-

ber of attempts to do this [44, 52, 78, 79, 91, 159, 244] these studies

have necessarily focused on a fairly narrow spectrum of architectures

and tools. They have typically been used to study routing architecture,

rather than logic block architecture. As an aside, the use of theory in

architecture research remains an open and possibly important question,

if some fundamental and usable theory can be created.

There are four aspects of an experimental ﬂow used to study archi-

tecture that need to be described when presenting experimental results:

(1) The depth of the CAD ﬂow. This depth represents how far

through synthesis, packing, placement, and routing the cir-

cuits are processed. (A survey of all these standard steps in

the FPGA CAD ﬂow has been covered in a previous issue

[54].) The deeper the CAD ﬂow, the more precise and believ-

able the results, but deeper ﬂows require a great deal more

development eﬀort and computation time.

(2) The quality of the CAD tools used. Low-quality tools can give

misleading architectural results. It is thus important to both

use the best tools available in CAD ﬂows and to realize that a

breakthrough in CAD tool development could dramatically

impact conclusions from experimental studies and possibly

the body of FPGA architectural knowledge. Yan et al. stud-

ied this issue [237] and described several situations where spe-

ciﬁc tools could create misleading architectural conclusions.

(3) The set of benchmark circuits used. The quality of results

depends on how representative the benchmark circuits are

with respect to typical circuits created by target users of a

device.

(4) The quality of the models and tools used to determine area,

speed, and power. For example, full timing analysis with

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