数字集成电路设计入门与Hspice模拟仿真

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"数字集成电路透视——一本深入探讨集成电路设计的书籍，适合有志于投身集成电路行业的读者。" 在《数字集成电路透视》这本书中，作者详细介绍了集成电路设计的基础知识和实用技巧，其中包括了对Hspice仿真工具的使用指南，这对于电路设计者来说是非常宝贵的经验分享。以下是其中的一些关键知识点：一、Hspice仿真入门 Hspice是一款广泛使用的电路仿真软件，对于电路设计和验证至关重要。在使用Hspice时，首先需要设置环境，通过执行`source/usr/eesww/HSPICE/98.2/bin/cshrc.meta`命令来配置环境变量。然后，你可以通过运行`hspice filename.sp > !filename.lis`来对输入文件进行仿真，这里的`filename.sp`是你的输入文件名，仿真结果会被重定向到`filename.lis`中。为了查看仿真波形，可以使用内置的波形查看器`awaves`。需要注意的是，输入文件必须具有`.sp`扩展名，以便波形查看器能正确识别。二、Netlist格式规范 Netlist是描述电路连接关系的文本文件，它定义了电路中的元件和它们之间的连接。在Hspice中，输入文件对大小写不敏感，第一条线通常用于注释。其他行可以通过`*`或`$`开头作为注释。所有非线性设备必须有`.MODEL`语句，以定义其行为模型。在命名规则上： 1. 设备名称可以包含字母、数字以及特定字符如!#$%*+-/<>[]_，且长度可达1024个字符。 2. 节点名称可以以字母、数字或#_!%开头，根据页码3-19的规则，尾部的字母在网名中会被忽略，例如，节点名`1A`和`1a`被视为相同。这些基础的Hspice使用技巧和Netlist格式规范是电路设计者必备的知识，它们帮助设计师准确地构建和仿真复杂的数字集成电路。通过学习《数字集成电路透视》，读者将能够更深入地理解集成电路设计的各个环节，从而提升设计能力和效率。

Section 1.3 Quality Metrics of a Digital Design 21

The text also addresses other compelling (global) issues in modern digital circuit

design such as power dissipation, interconnect, timing, and synchronization.

1.3Quality Metrics of a Digital Design

This section defines a set of basic properties of a digital design. These properties help to

quantify the quality of a design from different perspectives: cost, functionality, robustness,

performance, and energy consumption. Which one of these metrics is most important

depends upon the application. For instance, pure speed is a crucial property in a compute

server. On the other hand, energy consumption is a dominant metric for hand-held mobile

applications such as cell phones. The introduced properties are relevant at all levels of the

design hierarchy, be it system, chip, module, and gate. To ensure consistency in the defini-

tions throughout the design hierarchy stack, we propose a bottom-up approach: we start

with defining the basic quality metrics of a simple inverter, and gradually expand these to

the more complex functions such as gate, module, and chip.

1.3.1 Cost of an Integrated Circuit

The total cost of any product can be separated into two components: the recurring

expenses or the variable cost, and the non-recurring expenses or the fixed cost.

Fixed Cost

The fixed cost is independent of the sales volume, the number of products sold. An impor-

tant component of the fixed cost of an integrated circuit is the effort in time and man-

power it takes to produce the design. This design cost is strongly influenced by the com-

plexity of the design, the aggressiveness of the specifications, and the productivity of the

designer. Advanced design methodologies that automate major parts of the design process

can help to boost the latter. Bringing down the design cost in the presence of an ever-

increasing IC complexity is one of the major challenges that is always facing the semicon-

ductor industry.

Additionally, one has to account for the indirect costs, the company overhead that

cannot be billed directly to one product. It includes amongst others the company’s

research and development (R&D), manufacturing equipment, marketing, sales, and build-

ing infrastructure.

Variable Cost

This accounts for the cost that is directly attributable to a manufactured product, and is

hence proportional to the product volume. Variable costs include the costs of the parts

used in the product, assembly costs, and testing costs. The total cost of an integrated cir-

cuit is now

(1.1)cost per ICvariable cost per IC

fixed cost

volume

-----------------------





chapter1.fm Page 21 Friday, January 18, 2002 8:58 AM

22 INTRODUCTION Chapter 1

The impact of the fixed cost is more pronounced for small-volume products. This also

explains why it makes sense to have large design team working for a number of years on a

hugely successful product such as a microprocessor.

While the cost of producing a single transistor has dropped exponentially over the

past decades, the basic variable-cost equation has not changed:

(1.2)

As will be elaborated on in Chapter 2, the IC manufacturing process groups a number of

identical circuits onto a single wafer (Figure 1.9). Upon completion of the fabrication, the

wafer is chopped into dies, which are then individually packaged after being tested. We

will focus on the cost of the dies in this discussion. The cost of packaging and test is the

topic of later chapters.

The die cost depends upon the number of good die on a wafer, and the percentage of

those that are functional. The latter factor is called the die yield.

(1.3)

The number of dies per wafer is, in essence, the area of the wafer divided by the die

area.The actual situation is somewhat more complicated as wafers are round, and chips are

square. Dies around the perimeter of the wafer are therefore lost. The size of the wafer has

been steadily increasing over the years, yielding more dies per fabrication run. Eq. (1.3)

also presents the first indication that the cost of a circuit is dependent upon the chip

area—increasing the chip area simply means that less dies fit on a wafer.

The actual relation between cost and area is more complex, and depends upon the

die yield. Both the substrate material and the manufacturing process introduce faults that

can cause a chip to fail. Assuming that the defects are randomly distributed over the wafer,

and that the yield is inversely proportional to the complexity of the fabrication process, we

obtain the following expression of the die yield:

variable cost

cost of diecost of die testcost of packaging

final test yield

-------------------------------------------------------------------------------------------------------------------=

Figure 1.9 Finished wafer. Each

square represents a die - in this case

the AMD Duron™ microprocessor

(Reprinted with permission from AMD).

Individual die

cost of die

cost of wafer

dies per waferdie yield×

-------------------------------------------------------------=

chapter1.fm Page 22 Friday, January 18, 2002 8:58 AM

Section 1.3 Quality Metrics of a Digital Design 23

(1.4)

α is a parameter that depends upon the complexity of the manufacturing process, and is

roughly proportional to the number of masks. α = 3 is a good estimate for today’s complex

CMOS processes. The defects per unit area is a measure of the material and process

induced faults. A value between 0.5 and 1 defects/cm

is typical these days, but depends

strongly upon the maturity of the process.

Example 1.3 Die Yield

Assume a wafer size of 12 inch, a die size of 2.5 cm

, 1 defects/cm

, and α = 3. Determine the

die yield of this CMOS process run.

The number of dies per wafer can be estimated with the following expression, which

takes into account the lost dies around the perimeter of the wafer.

This means 252 (= 296 - 44) potentially operational dies for this particular example. The die

yield can be computed with the aid of Eq. (1.4), and equals 16%! This means that on the aver-

age only 40 of the dies will be fully functional.

The bottom line is that the number of functional of dies per wafer, and hence the

cost per die is a strong function of the die area. While the yield tends to be excellent for the

smaller designs, it drops rapidly once a certain threshold is exceeded. Bearing in mind the

equations derived above and the typical parameter values, we can conclude that die costs

are proportional to the fourth power of the area:

(1.5)

The area is a function that is directly controllable by the designer(s), and is the prime met-

ric for cost. Small area is hence a desirable property for a digital gate. The smaller the

gate, the higher the integration density and the smaller the die size. Smaller gates further-

more tend to be faster and consume less energy, as the total gate capacitance—which is

one of the dominant performance parameters—often scales with the area.

The number of transistors in a gate is indicative for the expected implementation

area. Other parameters may have an impact, though. For instance, a complex interconnect

pattern between the transistors can cause the wiring area to dominate. The gate complex-

ity, as expressed by the number of transistors and the regularity of the interconnect struc-

ture, also has an impact on the design cost. Complex structures are harder to implement

and tend to take more of the designers valuable time. Simplicity and regularity is a pre-

cious property in cost-sensitive designs.

1.3.2 Functionality and Robustness

A prime requirement for a digital circuit is, obviously, that it performs the function it is

designed for. The measured behavior of a manufactured circuit normally deviates from the

die yield 1

defects per unit areadie area×

-------------------------------------------------------------------------+





–

dies per wafer

π wafer diameter2⁄()

die area

-----------------------------------------------------------

π wafer diameter×

2die area×

---------------------------------------------–=

cost of die f die area()

chapter1.fm Page 23 Friday, January 18, 2002 8:58 AM

24 INTRODUCTION Chapter 1

expected response. One reason for this aberration are the variations in the manufacturing

process. The dimensions, threshold voltages, and currents of an MOS transistor vary

between runs or even on a single wafer or die. The electrical behavior of a circuit can be

profoundly affected by those variations. The presence of disturbing noise sources on or off

the chip is another source of deviations in circuit response. The word noise in the context

of digital circuits means “unwanted variations of voltages and currents at the logic

nodes.” Noise signals can enter a circuit in many ways. Some examples of digital noise

sources are depicted in Figure 1.10. For instance, two wires placed side by side in an inte-

grated circuit form a coupling capacitor and a mutual inductance. Hence, a voltage or cur-

rent change on one of the wires can influence the signals on the neighboring wire. Noise

on the power and ground rails of a gate also influences the signal levels in the gate.

Most noise in a digital system is internally generated, and the noise value is propor-

tional to the signal swing. Capacitive and inductive cross talk, and the internally-generated

power supply noise are examples of such. Other noise sources such as input power supply

noise are external to the system, and their value is not related to the signal levels. For these

sources, the noise level is directly expressed in Volt or Ampere. Noise sources that are a

function of the signal level are better expressed as a fraction or percentage of the signal

level. Noise is a major concern in the engineering of digital circuits. How to cope with all

these disturbances is one of the main challenges in the design of high-performance digital

circuits and is a recurring topic in this book.

The steady-state parameters (also called the static behavior) of a gate measure how

robust the circuit is with respect to both variations in the manufacturing process and noise

disturbances. The definition and derivation of these parameters requires a prior under-

standing of how digital signals are represented in the world of electronic circuits.

Digital circuits (DC) perform operations on logical (or Boolean) variables. A logical

variable x can only assume two discrete values:

x ∈ {0,1}

As an example, the inversion (i.e., the function that an inverter performs) implements the

following compositional relationship between two Boolean variables x and y:

y = x: {x = 0 ⇒ y = 1; x = 1 ⇒ y = 0} (1.6)

v(t)

i(t)

(a) Inductive coupling (b) Capacitive coupling

Figure 1.10 Noise sources in digital circuits.

noise

chapter1.fm Page 24 Friday, January 18, 2002 8:58 AM

Section 1.3 Quality Metrics of a Digital Design 25

A logical variable is, however, a mathematical abstraction. In a physical implemen-

tation, such a variable is represented by an electrical quantity. This is most often a node

voltage that is not discrete but can adopt a continuous range of values. This electrical volt-

age is turned into a discrete variable by associating a nominal voltage level with each logic

state: 1 ⇔ V

, 0 ⇔ V

, where V

and V

represent the high and the low logic levels,

respectively. Applying V

to the input of an inverter yields V

at the output and vice

versa. The difference between the two is called the logic or signal swing V

(1.7)

The Voltage-Transfer Characteristic

Assume now that a logical variable in serves as the input to an inverting gate that produces

the variable out. The electrical function of a gate is best expressed by its voltage-transfer

characteristic (VTC) (sometimes called the DC transfer characteristic), which plots the

output voltage as a function of the input voltage V

out

= f(V

). An example of an inverter

VTC is shown in Figure 1.11. The high and low nominal voltages, V

and V

, can

readily be identified—V

= f(V

) and V

= f(V

). Another point of interest of the

VTC is the gate or switching threshold voltage V

(not to be confused with the threshold

voltage of a transistor), that is defined as V

= f(V

). V

can also be found graphically at

the intersection of the VTC curve and the line given by V

out

= V

. The gate threshold volt-

age presents the midpoint of the switching characteristics, which is obtained when the out-

put of a gate is short-circuited to the input. This point will prove to be of particular interest

when studying circuits with feedback (also called sequential circuits).

Even if an ideal nominal value is applied at the input of a gate, the output signal

often deviates from the expected nominal value. These deviations can be caused by noise

or by the loading on the output of the gate (i.e., by the number of gates connected to the

output signal). Figure 1.12a illustrates how a logic level is represented in reality by a range

of acceptable voltages, separated by a region of uncertainty, rather than by nominal levels

()=

out

Figure 1.11 Inverter voltage-transfer

characteristic.

out

= V

chapter1.fm Page 25 Friday, January 18, 2002 8:58 AM

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