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SLVA680–February 2015
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Copyright © 2015, Texas Instruments Incorporated
ESD Protection Layout Guide
Application Report
SLVA680–February 2015
ESD Protection Layout Guide
Guy Yater ........................................................................................................... High Volume Linear
ABSTRACT
Successfully protecting a system against electrostatic discharge (ESD) is largely dependent on the printed
circuit board (PCB) design. While selecting the proper transient voltage suppressor (TVS) founds the basis
of an ESD protection strategy, its scope is not covered here. ESD selection guides are available in
Technical Documents at www.ti.com/esd for guidance in choosing the correct type of TVS diode for a
particular system. With the proper TVS selected, designing a PCB Layout that leverages the strategies
outlined in this ESD Layout Guide will provide the PCB designer with an avenue towards successfully
protecting a system against ESD.
Contents
1 Introduction ................................................................................................................... 1
2 PCB Layout Guidelines for Optimizing Dissipation of ESD ............................................................ 4
2.1 Optimizing Impedance for Dissipating ESD ..................................................................... 4
2.2 Limiting EMI from ESD............................................................................................. 5
2.3 Routing with VIAs ................................................................................................... 6
2.4 Optimizing Ground Schemes for ESD ........................................................................... 7
3 Conclusion .................................................................................................................... 9
Trademarks
1 Introduction
An ESD event rapidly forces current (see Figure 1), I
ESD
, into a system, usually through a user interface
such as a cable connection, or a human input device like a key on a keyboard. Protecting a system
against ESD using a TVS relies upon the TVS being able to shunt I
ESD
to ground. Optimizing a PCB
Layout for ESD suppression is largely dependant on designing the path to ground for I
ESD
with as little
impedance as possible. During an ESD event, the voltage presented to the protected integrated circuit
(Protected IC), V
ESD
, is a function of I
ESD
and the impedance presented to it. Since the designer has no
control over I
ESD
, lowering the impedance to ground is the primary means available for minimizing V
ESD
.
Lowering the impedance presents several challenges. Mainly, it cannot be of zero impedance, or the
signal line being protected would be shorted to ground. In order for the circuit to have a realistic
application, the protected line needs to be able to maintain some voltage, usually under a high
impedance to ground. This is where the TVS becomes applicable.