纳米级全芯片路由技术详解：集成电路设计后端必读

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"《全芯片纳米级布线技术》是一本专为集成电路设计领域后端工程师精心编撰的参考书籍，它深入探讨了纳米级电路设计中的关键技术。随着半导体工艺的进步，纳米级别的布线技术在现代集成电路中扮演着至关重要的角色，因为这直接影响到芯片的性能、功耗和集成密度。书名中的“Full-Chip Nanometer Routing Techniques”涵盖了从微观层面细致解析的布线策略，包括但不限于以下关键知识点： 1. 纳米级布线设计原理：书中详细介绍了如何在纳米尺度下实现高效的信号传输，如何优化路径长度、减少延迟，以及如何处理信号完整性问题，确保高速数据流在极小的空间内流畅传输。 2. 多层互连技术：随着芯片层数增加，多层布线结构成为必要。作者会讨论如何设计和优化多层布线网络，提高信号的质量和可靠性，同时考虑散热和电磁兼容性。 3. 信号噪声抑制：纳米级别的器件对噪声更为敏感，书中会涵盖低噪声设计技术和噪声源分析，如电源噪声、热噪声等，并提供有效的噪声抑制方法。 4. 电源和地线设计：电源和地线的设计是影响系统性能的重要因素，书中会介绍如何进行合理的电源分布网络和地线规划，以减小噪声耦合和电压波动。 5. 模拟电路与信号处理：对于包含模拟电路的系统，书中还会涉及模拟信号的布线技巧，如滤波器、放大器和接口电路的设计，确保这些电路与数字部分的协同工作。 6. 工艺相关挑战：随着技术节点的减小，材料、制造工艺的局限性和缺陷控制是必须考虑的问题。作者会探讨如何适应不断发展的CMOS工艺，解决工艺相关的路由问题。 7. CAD工具与方法：书中可能会涵盖当前的电子设计自动化（EDA）工具在纳米级布线中的应用，包括布线工具的优化和算法改进，以提升设计效率。这本书集合了多位专家的研究成果，例如关于射频发射器校准技术的《IQ Calibration Techniques for CMOS Radiotransceivers》，以及关于低功耗模拟电路设计和温度传感器的专著，为读者提供了全面的纳米级电路设计策略和技术指导。《全芯片纳米级布线技术》不仅是一本技术手册，还是一份前沿趋势的指南，对于从事集成电路设计的工程师来说，是不可或缺的专业参考资料。"

2 Chapter 1

Figure 1-1. Wire and Gate Delay in Al and Cu.

Figure 1-2. Cross-Coupling Between Neighboring Signal Affects Total Net Capacitance.

1. Introduction 3

2. ROUTING PROBLEMS

Routing is the process of finding the geometric layouts of all the nets.

The input of a routing problem is shown in the following:

(1) Routing area: the dimensions of the rectangular routing region and

the number of available routing layers

(2) Netlist: required interconnects as sets of connection points (“pins”)

on placed objects

(3) Design rules: specifications of the minimum and/or maximum values

allowed for wire width, wire spacing, via width, via spacing, etc.

(4) Pin locations: as determined by the placement or the floorplanning

process

(5) Obstacles: objects which wires cannot pass through, including placed

cells, IP blocks, pads, pre-routed wires, etc.

(6) Constraint-related parameters: such as the electrical parameters (e.g.,

RC constants) for performance and signal integrity constraints, thermal

parameters for the thermal constraints, etc.

The constraints of a general routing process usually include connection

rules and design rules [35]. Connection rules stipulate that (1) to prevent

open circuits, wires of the same net must be connected together and (2) to

avoid short circuits, wires of different nets must not overlap with each other

at the same layer. Design rules specify the sizes of the wires and vias (con-

nections between layers) and the minimum spacing between them according

to the available manufacturing technology. The objective of the routing prob-

lem depends on the circuit design. For general purpose chips, the objective is

usually the total wire length of all nets. For high-performance chips, the delay

of the circuit is minimized.

The continuous increasing system-on-chip (SoC) design complexity

imposes severe challenges for modern router design. As pointed out in Cong

et al. [31], a 2.5 × 2.5 cm

chip in the 70 nm technology may have over

360,000 horizontal and vertical routing tracks. In addition, the 90 nm

technology node has design rules in the high hundreds to low thousands,

whereas the forthcoming 65 nm node may have several thousand design

rules. To tackle the challenges, the routing frameworks are evolving from the

flat framework to the hierarchical and multilevel frameworks. We detail the

three routing frameworks in the following.

4 Chapter 1

consisting of global routing followed by detailed routing. Global routing first

partitions the routing area into tiles and decides tile-to-tile paths for all nets

while attempting to optimize some given objective functions (for example,

the overall wiring length and the timing constraints). Then, guided by the

results obtained in global routing, detailed routing assigns actual tracks and

vias for nets. Traditionally, many routing algorithms adopt a flat framework

that finds paths for nets directly. These algorithms can be classified into

sequential and concurrent approaches.

2.1.1 Sequential Approach

Perhaps the most straightforward strategy for routing is to select a

specific order and then to route nets sequentially in that order. The main

advantage of this approach is that the congestion information for previously

routed nets can be taken into consideration while routing a given net. The

drawback of sequential approach is that the quality of the routing solution

greatly depends on the order, and it is hard to find a good net ordering. Abel

[7] has concluded that there is no single net-ordering technique that performs

better than any other ordering method in all routing problems. Since the net-

ordering problem may cause unroutable nets, a rip-up/reroute procedure is

often used to refine the solution.

One basic subproblem in sequential routing is to find a path connecting

two pins in the presence of wiring blockages. Many algorithms have been

proposed for this subproblem, and these algorithms can be classified into

maze-searching and line-searching approaches.

(1) Maze Searching

Lee [68] proposed the first maze-searching algorithm, which adopts a two-

phase approach of wave propagation followed by retrace. In the wave pro-

pagation phase, starting from the source vertex A, the accumulated length from

the source to each vertex is labeled one by one according to the wavefront until

the target vertex B is reached. The shortest length path is then traced back from

B to A in the retrace phase. Figure 1-3 illustrates the process of Lee’s maze-

search algorithm. The Lee’s algorithm guarantees to find a connection between

requirements; therefore, it cannot be applied to large designs directly.

2.1 Flat Routing Framework

Research in VLSI routing has received much attention in the literature.

It is typically a very complex combinatorial problem. In order to make it

manageable, the routing problem is usually solved using a two-stage approach

in practice, the maze-searching algorithm is slow and has large memory

two terminals if it does exist and the connection is the shortest path. However,

1. Introduction 5

Figure 1-3. Maze Searching Example: (a) Wave Propagation and (b) Backtracking.

Soukup [92] combined breadth-first search and depth-first search approaches

to the wave propagation; with this approach, the maze-searching algorithm

can speed up 10–50 times than Lee’s algorithm, but the disadvantage is that

it does not guarantee to find the shortest path. Some techniques such as

starting point selection, double fanout, and framing are proposed to reduce

the search space of wave propagation and therefore to speed up the running

time considerably [87].

Although there exist some disadvantages in this maze-search method, the

maze-search approach still plays an important role and is usually incorpo-

rated into other existing routing algorithms. For example, Cong and Madden

[34] integrated maze routing and the iterative deletion technique to develop a

performance-driven multilayer area router for printed circuit board (PCB)

and multichip block (MCM) designs.

(2) Line Searching

As mentioned earlier, the major drawbacks of a maze-searching algorithm

are its high amount of memory required and long running time. The line-

search algorithm overcomes these drawbacks by using line segments to

represent the routing space and paths. Mikami and Tabuchi [81] proposed the

first line-search algorithm. As opposed to the maze-searching algorithm,

which mainly proceeds in a breadth-first manner, the line-searching algorithm

performs a depth-first search. The line-searching algorithm initially sets the

source S and the target T as base points, and then generates four (two

horizontal and two vertical) line segments passing through these base points.

These line segments are extended until they hit the design boundary or

Many efforts have attempted to improve its speed and memory usage.

Akers [8] proposed a coding sequence technique to reduce memory require-

ments. Instead of wavefront numbers, Hadlock [44] used detour numbers for

wave labeling to substantially reduce the search space and running time.

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