![](https://csdnimg.cn/release/download_crawler_static/87499726/bg4.jpg)
Information Classification: General
Introduction
Nowadays, demand for higher bandwidth DRAM continues to increase for high-
performance computing and graphic applications. One possible way to increase
bandwidth is to use many IOs along with high pin data rate as High Bandwidth Memory
(HBM) does [1]. While maintaining or increasing the number of IO lines over 1024,
HBM gen. 4 is expected to have 12.8-Gb/s pin data rate which is 4 times higher than the
data rate of HBM2E. To enable such high-rate data transmission in HBM, an equalizer is
required to alleviate inter-symbol interference (ISI) from its lossy on-interposer channel.
As shown in Fig. 1, we are highlighting the requirements of the equalizer for HBM:
(1) ISI cancellation effects; (2) low power consumption; (3) small area consumption as
well as maintaining the fine pitch of on-interposer channels. Especially, since a single
HBM provides a huge number of IO lines over 1024, small amount of increase in area or
power in IO circuits has a huge impact on the entire system. Therefore, small-area and
lower-power implementation is more demanding in HBM compared to other general
memory interfaces.
Continuous-time linear equalizer (CTLE) is a linear active filter that amplifies
signal around Nyquist frequency. CTLE can effectively reduce RC delay from on-
interposer channels while providing additional gain to the link [2]. However, it is
desirable to consider a design without CTLE that includes capacitors [2]-[3] or pre-
amplifier for high-density DQ path in HBM by considering their additional area and
power consumption. On the other hand, there is another active equalizer called decision-
feedback equalizer (DFE). It is a non-linear equalizer that employs previous decisions to
eliminate ISI caused by previous symbols on the current symbol to be detected. Contrary
to CTLE, DFE can be integrated into a RX sense amplifier for data acquisition and can be
directly used without a pre-amplifier [4]-[5]. A multi-tap DFE can be a solution to
alleviate long-tail ISI from on-interposer channels. However, it is challenging to close the
timing for feedback loop in 1 unit interval (UI) and DFE consumes considerable power as
the number of taps increase [6]-[8].
Other types of equalizers have been proposed for HBM DQ paths in a passive
manner. In [9], an on-die termination (ODT) was used for the DQ paths of HBM gen. 3.
By using terminations ranged from 60 W to 240 W, the eye diagrams were successfully
opened at the data rate of 6.4 Gb/s. Similarly, passive equalizers on the silicon interposer
also have been proposed for HBM [10]-[11]. Those on-interposer equalizers are shunt-R-
L-based design using the parasitic of the redistribution layer of interposer. The key point
of designing ODT or on-interposer passive equalizer is to lower their impedance enough
to decrease the RC delay from channel and it is effective in achieving wide timing
margin. However, it cancels ISI at the cost of low channel gain. Therefore, if only the
passive equalizer is used to cancel long-tail ISI, its impedance should be lower, which
results in lower eye height and makes data sampling difficult contradictorily.
In this paper, we firstly propose a hybrid equalizer which is co-designed with an on-
interposer passive equalizer and a 1-tap DFE. While the passive equalizer helps to
alleviates the overall long-tail ISI, 1-tap DFE cancels the remaining ISI. The proposed
equalizer mitigates the issue of chip-area overhead by including a passive equalizer on
interposer and a simple DFE on the chip side. By co-designing an on-interposer passive
equalizer and a DFE, the proposed hybrid equalizer compensates the disadvantage of 1-
tap DFE, or its poor performance over long-tail ISI, and that of passive equalizer, or gain