DS90C031B
SNLS051B –MARCH 1999–REVISED MARCH 2013
www.ti.com
Switching Characteristics
V
CC
= +5.0V, T
A
= +25°C
(1) (2) (3)
Symbol Parameter Conditions Min Typ Max Units
t
PHLD
Differential Propagation Delay High to Low R
L
= 100Ω, C
L
= 5 pF 1.0 2.0 3.0 ns
(Figure 3 and Figure 4)
t
PLHD
Differential Propagation Delay Low to High 1.0 2.1 3.0 ns
t
SKD
Differential Skew |t
PHLD
– t
PLHD
| 0 80 400 ps
t
SK1
Channel-to-Channel Skew
(4)
0 300 600 ps
t
TLH
Rise Time 0.35 1.5 ns
t
THL
Fall Time 0.35 1.5 ns
t
PHZ
Disable Time High to Z R
L
= 100Ω, C
L
= 5 pF 2.5 10 ns
(Figure 5 and Figure 6)
t
PLZ
Disable Time Low to Z 2.5 10 ns
t
PZH
Enable Time Z to High 2.5 10 ns
t
PZL
Enable Time Z to Low 2.5 10 ns
(1) All typicals are given for: V
CC
= +5.0V, T
A
= +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50Ω, t
r
≤ 6 ns, and t
f
≤ 6 ns.
(3) C
L
includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
Switching Characteristics
V
CC
= +5.0V ± 10%, T
A
= −40°C to +85°C
(1) (2) (3)
Symbol Parameter Conditions Min Typ Max Units
t
PHLD
Differential Propagation Delay High to Low R
L
= 100Ω, C
L
= 5 pF 0.5 2.0 3.5 ns
(Figure 3 and Figure 4)
t
PLHD
Differential Propagation Delay Low to High 0.5 2.1 3.5 ns
t
SKD
Differential Skew |t
PHLD
– t
PLHD
| 0 80 900 ps
t
SK1
Channel-to-Channel Skew
(4)
0 0.3 1.0 ns
t
SK2
Chip to Chip Skew
(5)
3.0 ns
t
TLH
Rise Time 0.35 2.0 ns
t
THL
Fall Time 0.35 2.0 ns
t
PHZ
Disable Time High to Z R
L
= 100Ω, C
L
= 5 pF 2.5 15 ns
(Figure 5 and Figure 6)
t
PLZ
Disable Time Low to Z 2.5 15 ns
t
PZH
Enable Time Z to High 2.5 15 ns
t
PZL
Enable Time Z to Low 2.5 15 ns
(1) All typicals are given for: V
CC
= +5.0V, T
A
= +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50Ω, t
r
≤ 6 ns, and t
f
≤ 6 ns.
(3) C
L
includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
(5) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
4 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90C031B
剩余18页未读，继续阅读
不觉明了
- 粉丝: 3275
- 资源: 5614
我的内容管理
收起
- 我的资源
快来上传第一个资源
我的收益 登录查看自己的收益
我的积分
登录查看自己的积分
我的C币
登录后查看C币余额
我的收藏 
我的下载 
下载帮助
会员权益专享
最新资源
- 电力电子系统建模与控制入门
- SQL数据库基础入门：发展历程与关键概念
- DC/DC变换器动态建模与控制方法解析
- 市***专有云IaaS服务：云主机与数据库解决方案
- 紫鸟数据魔方：跨境电商选品神器，助力爆款打造
- 电力电子技术：DC-DC变换器动态模型与控制
- 视觉与实用并重：跨境电商产品开发的六重价值策略
- VB.NET三层架构下的数据库应用程序开发
- 跨境电商产品开发：关键词策略与用户痛点挖掘
- VC-MFC数据库编程技巧与实现
- 亚马逊新品开发策略：选品与市场研究
- 数据库基础知识：从数据到Visual FoxPro应用
- 计算机专业实习经验与项目总结
- Sparkle家族轻量级加密与哈希：提升IoT设备数据安全性
- SQL数据库期末考试精选题与答案解析
- H3C规模数据融合：技术探讨与应用案例解析
资源上传下载、课程学习等过程中有任何疑问或建议，欢迎提出宝贵意见哦~我们会及时处理！
点击此处反馈
