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ADAU1787 Data Sheet
Rev. A | Page 18 of 280
Ball No. Mnemonic Type
1
Description
B4 DMIC_CLK0/MP7 D_IO Digital Microphone Clock Output 0.
Multipurpose I/O 7 (MP7).
B5 DMIC01/MP9 D_IO Digital Microphone Stereo Input 0 and Digital Microphone Stereo Input 1 (DMIC01).
Multipurpose I/O 9 (MP9).
B6 SDA/MISO D_IO
I
2
C Data (SDA). This pin is a bidirectional open-collector input. The line connected to this pin
must have a 2.0 kΩ pull-up resistor.
SPI Data Output (MISO). This SPI data output is used for reading back registers and memory
locations. This pin is tristated when an SPI read is not active.
SPI Clock (SCLK). This pin can either run continuously or can be gated off between SPI
transactions.
B7 SCL/SCLK D_IN
I
2
C Clock (SCL). This pin is always an open-collector input when the device is in I
2
C control
mode. When the device is in self-boot mode, this pin is an open-collector output (I
2
C master).
The line connected to this pin must have a 2.0 kΩ pull-up resistor.
SPI Clock (SCLK). This pin can either run continuously or be gated off between SPI transactions.
C1 HPOUTP1/LOUTP1 A_OUT Headphone Output Noninverted Channel 1 (HPOUTP1).
Line Output Noninverted Channel 1 (LOUTP1).
C2 DMIC_CLK1/MP8 D_IO Digital Microphone Clock Output 1 (DMIC_CLK1).
Multipurpose I/O 8 (MP8).
C3 SDATAO_1/MP5 D_IO Serial Audio Port 1 Output Data (SDATAO_1).
Multipurpose I/O 5 (MP5).
C4 SDATAI_1/MP6 D_IO Serial Audio Port 1 Input Data (SDATAI_1).
Multipurpose I/O 6 (MP6).
C5 BCLK_1/MP4 D_IO Serial Audio Port 1 Bit Clock (BCLK_1).
Multipurpose I/O 4 (MP4).
C6
ADDR0/SS
D_IN I
2
C Address 0 (ADDR0).
SPI Latch Signal (SS). This pin must go low at the beginning of an SPI transaction and high at
the end of a transaction. Each SPI transaction may take a different number of SCLK cycles to
complete, depending on the address and read/write bit that are sent at the beginning of the
SPI transaction.
C7 ADDR1/MOSI D_IN I
2
C Address 1 (ADDR1).
SPI Data Input (MOSI).
D1 HPVDD PWR
Headphone Amplifier Power, 1.8 V Analog Supply. Decouple this pin to HPGND with a 0.1 F
capacitor. The PCB trace to this pin must be wider to supply the higher current necessary for
driving the headphone outputs.
D2 HPOUTN1/LOUTN1 A_OUT Headphone Output Inverted Channel 1 (HPOUTN1).
Line Output Inverted Channel 1 (LOUTN1).
D3 SW_EN/MP12 D_IN I
2
C/SPI Enable (SW_EN). Connect this pin to DGND.
Multipurpose I/O 12 (MP12).
D4
PD
D_IN
Active Low Power-Down. All digital and analog circuits are powered down. There is an
internal pull-down resistor on this pin. Therefore, the ADAU1787 is held in power-down
mode if the input signal is floating while power is applied to the supply pins.
D5 FSYNC_1/MP3 D_IO Serial Audio Port 1 Frame Sync/Left Right Clock (FSYNC_1).
Multipurpose I/O 3 (MP3).
D6 SELFBOOT/MP11 D_IN
Self Boot. Connect this pin to IOVDD at power-up to enable the self boot mode. Otherwise,
set this pin to DGND at startup.
Multipurpose I/O 11 (MP11).
D7 MICBIAS0 A_OUT Bias Voltage for Electret Microphone 0. Decouple this pin with a 1 µF capacitor.
E1 HPGND PWR Headphone Amplifier Ground.
E2 HPOUTP0/LOUTP0 A_OUT Headphone Output Noninverted Channel 0 (HPOUTP0).
Line Output Noninverted Channel 0 (LOUTP0).