Datasheet 16 of 164 002-18043 Rev. *I
October 13, 2021
32-bit Arm
®
Cortex
®
-M4F Microcontroller TRAVEO™ T2G Family
CYT2B7
Functional description
3.4.1 Port nomenclature
Px.y describes a particular bit “y” available within an I/O port “x.”
For example, P4.2 reads “port 4, bit 2”.
Each I/O implements the following:
• Programmable drive mode
- High impedance
- Resistive pull-up
- Resistive pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up or pull-down
- Weak pull-up or pull-down
CYT2B7 has two types of programmable I/Os: GPIO standard and GPIO Enhanced.
• GPIO Standard (GPIO_STD)
Supports standard automotive signaling across the 2.7-V to 5.5-V V
DDIO
range. GPIO Standard I/Os have multi-
ple configurable drive levels, drive modes, and selectable input levels.
• GPIO Enhanced (GPIO_ENH)
Supports extended functionality automotive signalling across the 2.7-V to 5.5-V V
DDIO
range with higher cur-
rents at lower voltages (full I
2
C timing support, slew-rate control).
Both GPIO_STD and GPIO_ENH implement the following:
• Configurable input threshold (CMOS, TTL, or Automotive)
• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)
• Analog input mode (input and output buffers disabled)
3.4.2 Smart I/O
Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals
coming into the chip. CYT2B7 has five Smart I/O blocks. Operation can be synchronous or asynchronous and the
blocks operate in all device power modes except for the Hibernate mode.
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