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瑞萨RX24T微控制器硬件用户手册
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"瑞萨RX24T用户手册,包含了该32位微控制器的硬件使用说明,属于RX家族中的RX200系列。文档日期为2017年4月,版本2.00。请注意,文档中的产品信息和规格可能会随瑞萨电子的更新而变化,建议通过官方网站获取最新信息。手册中的电路、软件和其他相关信息仅用于说明半导体产品的操作和应用示例,用户在产品或系统设计中使用这些内容需自担风险,瑞萨电子不承担由此产生的任何损失或损害的责任。"
瑞萨RX24T是一款32位微控制器,是瑞萨电子RX200系列的一部分,特别适用于需要高效能和低功耗的嵌入式应用。RX24T芯片的设计目标可能是工业控制、物联网(IoT)设备、自动化系统以及各种需要实时处理能力的场合。
该用户手册详细介绍了RX24T微控制器的硬件特性,包括:
1. 内核架构:RX24T可能采用了高效的RX内核,提供高性能计算能力,支持指令集优化,以实现快速响应和低功耗运行。
2. 存储器配置:可能包含闪存、SRAM以及其他类型的存储器,用于存储程序代码、数据和堆栈。
3. 外设接口:RX24T可能集成了多种外设接口,如UART、SPI、I2C、CAN、USB、以太网等,以满足不同通信需求。
4. 定时器和计数器:可能包括多个定时器和计数器单元,用于脉冲控制、时间间隔测量等应用。
5. 模数转换器(ADC)和数模转换器(DAC):可能提供了高精度的模拟输入/输出功能,适用于信号采集和处理。
6. 模块化外设:可能包含PWM模块、比较器、看门狗定时器等,方便系统设计。
7. 电源管理:可能具备灵活的电源管理模式,以适应不同功耗要求的应用场景。
8. 异常处理和中断系统:支持多种中断源,实现快速响应和高效任务调度。
手册还会详细介绍如何使用这些硬件资源,包括初始化设置、编程指导、调试工具的使用方法以及错误处理策略。此外,用户可以了解到如何将提供的电路、软件示例集成到自己的设计方案中,以及如何利用瑞萨提供的开发工具进行项目开发。
瑞萨电子作为知名的半导体制造商,其产品通常具有良好的兼容性和扩展性,RX24T用户手册不仅对单个芯片进行了详细解释,还可能涵盖了与之相关的生态系统,如开发板、软件开发工具链、RTOS支持、库函数等。
瑞萨RX24T用户手册是一份全面的技术参考资料,对于想要利用RX24T微控制器开发产品的工程师来说,它是不可或缺的学习和设计指南。通过深入理解和实践手册中的内容,用户能够充分利用RX24T的特性,构建出高效可靠的嵌入式系统。
14.4.1.2 Operation of Status Flags for Level-Detected Interrupts ................................................ 275
14.4.2 Enabling and Disabling Interrupt Sources ................................................................................ 276
14.4.3 Selecting Interrupt Request Destinations ................................................................................. 277
14.4.4 Determining Priority ................................................................................................................. 278
14.4.5 Multiple Interrupts .................................................................................................................... 278
14.4.6 Fast Interrupt ............................................................................................................................. 278
14.4.7 Digital Filter ............................................................................................................................. 279
14.4.8 External Pin Interrupts .............................................................................................................. 279
14.5 Non-maskable Interrupt Operation .................................................................................................... 280
14.6 Return from Power-Down States ....................................................................................................... 281
14.6.1 Return from Sleep Mode or Deep Sleep Mode ........................................................................ 281
14.6.2 Return from Software Standby Mode ....................................................................................... 281
14.7 Usage Note ........................................................................................................................................ 282
14.7.1 Note on WAIT Instruction Used with Non-Maskable Interrupt ............................................... 282
15. Buses ........................................................................................................................................... 283
15.1 Overview ........................................................................................................................................... 283
15.2 Description of Buses .......................................................................................................................... 285
15.2.1 CPU Buses ................................................................................................................................ 285
15.2.2 Memory Buses .......................................................................................................................... 285
15.2.3 Internal Main Buses .................................................................................................................. 285
15.2.4 Internal Peripheral Buses .......................................................................................................... 286
15.2.5 Write Buffer Function (Internal Peripheral Bus) ...................................................................... 287
15.2.6 Parallel Operation ..................................................................................................................... 288
15.2.7 Restrictions ............................................................................................................................... 289
15.3 Register Descriptions ......................................................................................................................... 290
15.3.1 Bus Error Status Clear Register (BERCLR) ............................................................................. 290
15.3.2 Bus Error Monitoring Enable Register (BEREN) .................................................................... 290
15.3.3 Bus Error Status Register 1 (BERSR1) .................................................................................... 291
15.3.4 Bus Error Status Register 2 (BERSR2) .................................................................................... 291
15.3.5 Bus Priority Control Register (BUSPRI) .................................................................................. 292
15.4 Bus Error Monitoring Section ........................................................................................................... 294
15.4.1 Types of Bus Error ........................................................................................................
......
..... 294
15.4.1.1 Illegal Address Access .................................................................................................... 294
15.4.1.2 Timeout ............................................................................................................................ 294
15.4.2 Operations When a Bus Error Occurs ...................................................................................... 295
15.4.3 Conditions Leading to Bus Errors ............................................................................................ 295
15.5 Interrupt ............................................................................................................................................. 296
15.5.1 Interrupt Source ........................................................................................................................ 296
16. Memory-Protection Unit (MPU) .................................................................................................... 297
16.1 Overview ........................................................................................................................................... 297
16.1.1 Types of Access Control ........................................................................................................... 299
16.1.2 Regions for Access Control ...................................................................................................... 299
16.1.3 Background Region .................................................................................................................. 299
16.1.4 Overlap between Regions ......................................................................................................... 299
16.1.5 Instructions and Data that Span Regions .................................................................................. 299
16.2 Register Descriptions ......................................................................................................................... 300
16.2.1 Region-n Start Page Number Register (RSPAGEn) (n = 0 to 7) ............................................. 300
16.2.2 Region-n End Page Number Register (REPAGEn) (n = 0 to 7) .............................................. 301
16.2.3 Memory-Protection Enable Register (MPEN) ......................................................................... 302
16.2.4 Background Access Control Register (MPBAC) ..................................................................... 303
16.2.5 Memory-Protection Error Status-Clearing Register (MPECLR) ............................................. 304
16.2.6 Memory-Protection Error Status Register (MPESTS) ............................................................. 305
16.2.7 Data Memory-Protection Error Address Register (MPDEA) ................................................... 306
16.2.8 Region Search Address Register (MPSA) ................................................................................ 307
16.2.9 Region Search Operation Register (MPOPS) ........................................................................... 307
16.2.10 Region Invalidation Operation Register (MPOPI) ................................................................... 308
16.2.11 Instruction-Hit Region Register (MHITI) ................................................................................ 309
16.2.12 Data-Hit Region Register (MHITD) ......................................................................................... 311
16.3 Functions ........................................................................................................................................... 313
16.3.1 Memory Protection ................................................................................................................... 313
16.3.2 Region Search ........................................................................................................................... 313
16.3.3 Protection of Registers Related to the Memory-Protection Unit .............................................. 313
16.3.4 Flow for Determination of Access by the Memory-Protection Function ................................. 314
16.4 Procedures for Using Memory Protection ......................................................................................... 316
16.4.1 Setting Access-Control Information ......................................................................................... 316
16.4.2 Enabling Memory Protection .................................................................................................... 316
16.4.3 Transition to User Mode ........................................................................................................... 316
16.4.4 Processing in Response to Memory-Protection Errors ............................................................. 316
17. Data Transfer Controller (DTCa) .................................................................................................. 318
17.1 Overview ........................................................................................................................................... 318
17.2 Register Descriptions ......................................................................................................................... 320
17.2.1 DTC Mode Register A (MRA) ................................................................................................. 320
17.2.2 DTC Mode Register B (MRB) ................................................................................................. 321
17.2.3 DTC Transfer Source Register (SAR)
.....
................................................................................. 322
17.2.4 DTC Transfer Destination Register (DAR) .............................................................................. 322
17.2.5 DTC Transfer Count Register A (CRA) ................................................................................... 323
17.2.6 DTC Transfer Count Register B (CRB) ................................................................................... 324
17.2.7 DTC Control Register (DTCCR) .............................................................................................. 324
17.2.8 DTC Vector Base Register (DTCVBR) ................................................................................... 325
17.2.9 DTC Address Mode Register (DTCADMOD) ......................................................................... 325
17.2.10 DTC Module Start Register (DTCST) ...................................................................................... 326
17.2.11 DTC Status Register (DTCSTS) ............................................................................................... 327
17.3 Request Sources ................................................................................................................................. 328
17.3.1 Allocating Transfer Information and DTC Vector Table ......................................................... 328
17.4 Operation ........................................................................................................................................... 330
17.4.1 Transfer Information Read Skip Function ................................................................................ 332
17.4.2 Transfer Information Write-Back Skip Function ..................................................................... 333
17.4.3 Normal Transfer Mode ............................................................................................................. 334
17.4.4 Repeat Transfer Mode .............................................................................................................. 335
17.4.5 Block Transfer Mode ................................................................................................................ 336
17.4.6 Chain Transfer .......................................................................................................................... 337
17.4.7 Operation Timing ..................................................................................................................... 338
17.4.8 Execution Cycles of the DTC ................................................................................................... 341
17.4.9 DTC Bus Mastership Release Timing ...................................................................................... 341
17.5 DTC Setting Procedure ...................................................................................................................... 342
17.6 Examples of DTC Usage ................................................................................................................... 343
17.6.1 Normal Transfer ....................................................................................................................... 343
17.6.2 Chain Transfer When the Counter is 0 ..................................................................................... 344
17.7 Interrupt Source ................................................................................................................................. 345
17.8 Low Power Consumption Function ................................................................................................... 346
17.9 Usage Notes ....................................................................................................................................... 347
17.9.1 Start Address of Transfer Information ...................................................................................... 347
17.9.2 Allocating Transfer Information ............................................................................................... 347
18. I/O Ports ....................................................................................................................................... 348
18.1 Overview ........................................................................................................................................... 348
18.2 I/O Port Configuration ....................................................................................................................... 350
18.3 Register Descriptions ......................................................................................................................... 353
18.3.1 Port Direction Register (PDR) .................................................................................................. 353
18.3.2 Port Output Data Register (PODR) .......................................................................................... 354
18.3.3 Port Input Data Register (PIDR) .............................................................................................. 355
18.3.4 Port Mode Register (PMR) ....................................................................................................... 356
18.3.5 Open Drain Control Register 0 (ODR0) ................................................................................... 357
18.3.6 Open Drain Control Register 1 (ODR1) ................................................................................... 358
18
.3.7
Pull-Up Control Register (PCR) ............................................................................................... 359
18.3.8 Drive Capacity Control Register (DSCR) ................................................................................ 360
18.4 Initialization of the Port Direction Register (PDR) ........................................................................... 361
18.5 Handling of Unused Pins ................................................................................................................... 363
19. Multi-Function Pin Controller (MPC) ............................................................................................ 364
19.1 Overview ........................................................................................................................................... 364
19.2 Register Descriptions ......................................................................................................................... 371
19.2.1 Write-Protect Register (PWPR) ................................................................................................ 371
19.2.2 P0n Pin Function Control Register (P0nPFS) (n = 0 to 2) ....................................................... 372
19.2.3 P1n Pin Function Control Register (P1nPFS) (n = 0, 1) .......................................................... 373
19.2.4 P2n Pin Function Control Register (P2nPFS) (n = 0 to 4) ....................................................... 375
19.2.5 P3n Pin Function Control Register (P3nPFS) (n = 0 to 3) ....................................................... 377
19.2.6 P4n Pin Function Control Register (P4nPFS) (n = 0 to 7) ....................................................... 379
19.2.7 P5n Pin Function Control Register (P5nPFS) (n = 0 to 5) ....................................................... 380
19.2.8 P6n Pin Function Control Register (P6nPFS) (n = 0 to 5) ....................................................... 381
19.2.9 P7n Pin Function Control Register (P7nPFS) (n = 0 to 6) ....................................................... 382
19.2.10 P8n Pin Function Control Register (P8nPFS) (n = 0 to 2) ....................................................... 383
19.2.11 P9n Pin Function Control Register (P9nPFS) (n = 0 to 6) ....................................................... 384
19.2.12 PAn Pin Function Control Register (PAnPFS) (n = 0 to 5) ..................................................... 385
19.2.13 PBn Pin Function Control Register (PBnPFS) (n = 0 to 7) ...................................................... 387
19.2.14 PDn Pin Function Control Register (PDnPFS) (n = 0 to 7) ..................................................... 389
19.2.15 PEn Pin Function Control Register (PEnPFS) (n = 0 to 5) ...................................................... 391
19.3 Usage Notes ....................................................................................................................................... 393
19.3.1 Procedure for Specifying Input/Output Pin Function ............................................................... 393
19.3.2 Notes on MPC Register Setting ................................................................................................ 393
19.3.3 Note on Using Analog Functions ............................................................................................. 394
19.3.4 Note on PB1/PB2 Pin Input Level ............................................................................................ 394
19.3.5 Notes when Switching to the General Input and Output Ports when a Source is Generated
(Only for Chip Version B) ........................................................................................................ 394
19.3.6 Notes on Inversion of the Input and Output Pins of the MTU and GPT
(Only for Chip Version B) ........................................................................................................ 395
20. Multi-Function Timer Pulse Unit 3 (MTU3d) ................................................................................. 397
20.1 Overview ........................................................................................................................................... 397
20.2 Register Descriptions ......................................................................................................................... 403
20.2.1 Timer Control Register (TCR) ................................................................................................. 403
20.2.2 Timer Control Register 2 (TCR2) ............................................................................................ 405
20.2.3 Timer Mode Register 1 (TMDR1) ............................................................................................ 409
20.2.4 Timer Mode Registers 2 (TMDR2A, TMDR2B) ..................................................................... 411
20.2.5 Timer Mode Register 3 (TMDR3) ............................................................................................ 412
20.2.6 Timer I/O Control Register (TIOR) ......................................................................................
.... 413
20.2.7
Timer Compare Ma
tch Clear Register (TCNTCMPCLR) ....................................................... 430
20.2.8 Timer Interrupt Enable Register (TIER) .................................................................................. 431
20.2.9 Timer Status Register (TSR) .................................................................................................... 434
20.2.10 Timer Buffer Operation Transfer Mode Register (TBTM) ...................................................... 435
20.2.11 Timer Input Capture Control Register (TICCR) ...................................................................... 436
20.2.12 Timer Synchronous Clear Register (TSYCR) .......................................................................... 437
20.2.13 Timer Counter (TCNT) ............................................................................................................ 438
20.2.14 Timer Longword Counter (TCNTLW) ..................................................................................... 438
20.2.15 Timer General Register (TGR) ................................................................................................. 439
20.2.16 Timer Longword General Registers (TGRALW, TGRBLW) .................................................. 439
20.2.17 Timer Start Registers (TSTRA, TSTRB, TSTR) ..................................................................... 440
20.2.18 Timer Synchronous Registers (TSYRA, TSYRB) ................................................................... 442
20.2.19 Timer Counter Synchronous Start Register (TCSYSTR) ......................................................... 444
20.2.20 Timer Read/Write Enable Registers (TRWERA, TRWERB) .................................................. 446
20.2.21 Timer Output Master Enable Registers (TOERA, TOERB) .................................................... 447
20.2.22 Timer Output Control Registers 1 (TOCR1A, TOCR1B) ........................................................ 449
20.2.23 Timer Output Control Registers 2 (TOCR2A, TOCR2B) ........................................................ 451
20.2.24 Timer Output Level Buffer Registers (TOLBRA, TOLBRB) ................................................. 454
20.2.25 Timer Gate Control Registers (TGCRA, TGCRB) .................................................................. 455
20.2.26 Timer Subcounters (TCNTSA, TCNTSB) ............................................................................... 456
20.2.27 Timer Period Data Registers (TCDRA, TCDRB) .................................................................... 456
20.2.28 Timer Period Buffer Registers (TCBRA, TCBRB) .................................................................. 457
20.2.29 Timer Dead Time Data Registers (TDDRA, TDDRB) ............................................................ 457
20.2.30 Timer Dead Time Enable Registers (TDERA, TDERB) ......................................................... 458
20.2.31 Timer Buffer Transfer Set Registers (TBTERA, TBTERB) .................................................... 459
20.2.32 Timer Waveform Control Registers (TWCRA, TWCRB) ....................................................... 460
20.2.33 Noise Filter Control Register n (NFCRn) (n = 0 to 4, 6, 7, 9, C) ............................................. 462
20.2.34 Noise Filter Control Register 5 (NFCR5) ................................................................................. 464
20.2.35 Timer A/D Converter Start Request Control Register (TADCR) ............................................ 465
20.2.36 Timer A/D Converter Start Request Cycle Set Registers (TADCORA, TADCORB) ............. 469
20.2.37 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA, TADCOBRB) .................................................................................................. 469
20.2.38 Timer Interrupt Skipping Mode Registers (TITMRA, TITMRB) ............................................ 470
20.2.39 Timer Interrupt Skipping Set Registers 1 (TITCR1A, TITCR1B) ........................................... 471
20.2.40 Timer Interrupt Skipping Counters 1 (TITCNT1A, TITCNT1B) ............................................ 473
20.2.41 Timer Interrupt Skipping Set Registers 2 (TITCR2A, TITCR2B) ........................................... 475
20.2.42 Timer Interrupt Skipping Counters 2 (TITCNT2A, TITCNT2B) ............................................ 477
20.2.43 A/D Conversion Start Request Select Register 0 (TADSTRGR0) ........................................... 478
20.2.44 A/D Conversion Start Request Select Register 1 (TADSTRGR1) ........................................... 479
20.3 Operation ........................................................................................................................................... 480
20.3.1 Basic Functions ......................................................................................................................... 480
20.3.2 Synchronous Operation ............................................................................................................ 486
20.3.3 Buffer Operation ....................................................................................................................... 488
20.3.4 Cascaded Operation .................................................................................................................. 492
20.3.5 PWM Modes ...............................................
................................................................
......
........ 497
20.3.6 Phase Counting Mode ............................................................................................................... 502
20.3.6.1 16-Bit Phase Counting Mode .......................................................................................... 502
20.3.6.2 Cascade Connection 32-Bit Phase Counting Mode ......................................................... 513
20.3.7 Reset-Synchronized PWM Mode ............................................................................................. 514
20.3.8 Complementary PWM Mode .................................................................................................... 517
20.3.9 A/D Converter Start Request Delaying Function ..................................................................... 559
20.3.10 Synchronous Operation of MTU0 to MTU4, MTU6, MTU7, and MTU9 ............................... 565
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