IBM OPB总线架构规范2.1：最新版本与注意事项

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On-Chip Peripheral Bus (OPB) Architecture Specifications Version 2.1 是一份针对IBM OPB总线的详细技术文档，发布于2001年4月，适用于当时的OPB架构，直到后续版本或应用笔记中另有指示。这份规范主要关注片上外围设备总线的设计和实现，旨在定义接口标准、数据传输协议以及系统级集成的硬件与软件交互方式。该文档的核心内容包括： 1. **设计目标**：OPB架构的目的是为了提高芯片内的通信效率，通过在单个芯片内集中管理外围设备，减少外部接口的需求，从而简化系统设计，提升性能和功耗效率。 2. **接口规范**：详细说明了OPB的物理层、数据传输协议（如地址映射、时序规定、错误检测和校验机制）以及信号线定义。这涉及到如何在处理器和外围模块之间建立可靠的数据交换路径。 3. **功能划分**：明确了OPB的组成部分，如数据总线、控制信号线、地址空间管理和中断管理，以确保各模块间的同步工作。 4. **兼容性和限制**：强调了该规范仅适用于IBM OPB，且可能存在地域性法律限制，例如某些国家可能不接受某些免责声明。此外，IBM并不保证产品适用于所有特定用途，并承认可能存在技术不准确或打印错误。 5. **法律责任**：作为"as is"提供，IBM不对本手册的任何部分提供任何形式的保证，包括但不限于适销性和特定目的的适合性。某些司法管辖区可能不允许某些免责声明，这意味着某些条款可能对用户不适用。 6. **更新维护**：指出文档中的信息可能包含临时的技术不准确或排版错误，IBM会定期更新这些资料，以反映最新的设计变更。 On-Chip Peripheral Bus Architecture Specifications Version 2.1是开发人员、硬件工程师和系统设计师在设计和实现基于IBM OPB的嵌入式系统时的重要参考，提供了构建高效、兼容且可扩展的片上外围设备通信基础设施的蓝图。

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On-Chip Peripheral Bus Version 2.1

Figure 1 demonstrates how the on-chip peripheral bus is interconnected for the purpose of

Core+ASIC development or system-on-a-chip design.

As shown in Figure 1, the on-chip bus structure provides a link between the processor core and other

peripherals which consist of PLB and OPB master and slave devices.

The processor local bus (PLB) is the high performance bus used to access memory through the bus

interface units. The two bus interface units shown above: external peripheral controller and memory

controller are the PLB slaves. The processor core has two PLB master connections, one for

instruction cache and one for data cache. Attached to the PLB is also the direct memory access

(DMA) controller, which is a PLB master device used in data intensive applications to improve data

transfer performance.

Lower performance peripherals (such as OPB master, slave, and other internal peripherals) are

attached to the on-chip peripheral bus (OPB). A bridge is provided between the PLB and OPB to

enable data transfer by PLB masters to and from OPB slaves. The PLB to OPB bridge is a slave on

the PLB and a master on the OPB. A bridge is provided between the OPB and PLB to enable data

transfer by OPB masters to and from PLB slaves. The OPB to PLB bridge is a slave on the OPB and

a master on the PLB. DMA slave peripherals are also supported on the OPB.

The device control register (DCR) bus is used primarily for accessing status and control registers

within the various PLB and OPB masters and slaves. It is meant to off-load the PLB from the lower

performance status and control register read and write transfers. The DCR bus architecture allows

data transfers to occur independent of PLB and OPB transfers.

On-Chip Peripheral Bus

Processor Local Bus

OPB

PLB

OPB

Internal

OPB

Master

Slave

Peripheral

PLB to OPB

Bridge

Figure 1. On-chip Peripheral Bus Interconnection

DCR Bus

Arbiter

Processor Core

Data Instruction

Cache UnitCache Unit

OPB to PLB

Bridge

Memory Controller

SDRAM

Controller

External Peripheral Controller

External

Peripheral

External

Bus Master

DMA

Controller

DCR Bus

SRAM

ROM

DCR Bus

On-Chip Peripheral Bus Version 2.1

Chapter 2. OPB Signals

OPB signals can be grouped under the following categories:

– Arbitration Signals

– Bus Signals

– Data Transfer Control Signals

– DMA Peripheral Support Signals (Optional)

2.1 Signal Naming Conventions

The implementation of the OPB consists of an OPB arbiter, and a combination of OPB master and

slave devices, connected at the chip level by bus logic (AND and OR gates). Slaves which are

connected to the OPB use the following naming convention:

• Signals which are outputs of the OPB bus logic and inputs to the master and slave devices are

preﬁxed with OPB_. There is only one output of the bus logic for each one of these signals and it is

received as an input by each relevant device attached on the OPB. For example, OPB_RNW is an

output of the OPB bus logic and is an input to each slave attached to the OPB.

• Signals which are outputs of the OPB slaves and inputs to the OPB bus logic are preﬁxed with

Sln_. Each slave has its own output which is an input to the OPB bus logic, where it is logically

OR’ed together to form a single signal. The slaves must ensure that these signals are driven to a

logic ‘0’ when they are not involved in a transfer on the OPB (with the exception of Sln_DBus, which

need not be driven to a “0” when inactive, but which is qualiﬁed with Sln_DBusEn). For example,

Sln_xferAck is an output of each slave attached to the OPB, there are multiple Sln_xferAck inputs

to the OPB bus logic, and they are OR’ed together to form OPB_xferAck, which is output to all OPB

masters.

Each master is attached directly to the OPB bus logic with its own address, read data, and write data

buses and control signals, and these signals use the following naming convention:

• Signals which are driven by a master as an input to the OPB bus logic are pre-ﬁxed with Mn_. For

example, Mn_request signal when implemented would result in M0_request, M1_request, etc., up

to the maximum number of masters supported (implementation dependent).

• Signals which are driven by the OPB arbiter to a speciﬁc master have a preﬁx OPB_Mn to indicate

that this signal is from the OPB arbiter to a speciﬁc master (i.e. OPB_MnGrant). The OPB arbiter

provides an output for this signal for each master attached to the bus. For example, the

OPB_MnGrant signal, when implemented would result in OPB_M0Grant, OPB_M1Grant, etc., up

to the maximum number of masters supported (implementation dependent).

• Signals which are driven by the OPB bus logic to all master and slave devices are preﬁxed with

OPB_. There is only one output of the OPB bus logic for each one of these signals and it is

received as an input by each relevant device attached on the OPB. For example, OPB_select is an

output of the OPB bus logic and is an input to each slave device attached to the OPB.

Table 4 provides a summary of all OPB input/output signals in alphabetical order, the interfaces under

which they are grouped, followed by a brief description and page reference for detailed functional

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