AC‘97音频编解码器规范详解

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"Audio Codec ‘97 Component Specification, Revision 2.3" 音频编码器‘97（AC ‘97）规格是针对主流个人计算机系统中实现音频和调制解调器I/O功能的一种专门设计的架构和数字接口（AC-link）。这个规范定义了AC ‘97架构的核心组成部分，但并未详细说明与之配合使用的AC ‘97数字控制器（有时称为DC ‘97），因为该控制器在功能和实现上通常存在差异，但需符合此规格以确保AC ‘97兼容性。 AC ‘97规范自1997年首次发布以来，经过多次修订，其中Revision 2.3是本文档的一个重要版本，发布于2002年4月。这一版本包含了对早期1.0版的改进和扩展，以适应不断发展的个人计算机音频技术的需求。此规格文档中包含了关于AC ‘97组件的关键技术细节，例如其数字接口（AC-link）的设计，它允许音频和调制解调器芯片之间高效、低延迟的数据传输。AC ‘97架构通常由两部分组成：音频编解码器和数字控制器。编解码器负责音频信号的模拟与数字转换，而数字控制器则管理接口和系统级通信。 Intel公司作为AC ‘97规范的提供者，明确表示不对文档中的错误或遗漏承担责任，也不承诺更新其中的信息。此外，Intel不提供任何明示或暗示的保证，包括但不限于适销性、特定用途适用性的保证，以及与实施本规格相关的任何知识产权侵权责任的豁免。对于希望使用AC ‘97规格的任何感兴趣方，Intel提供了免版税的有限许可。如果想要获取关于Audio Codec '97的特定许可条款，可以联系Intel的audio97@intel.com。请注意，尽管Intel的许可是免版税的，但实际实现该规格的产品可能仍需考虑潜在的知识产权侵权问题。最后，Intel保留所有版权，2002年版的AC ‘97组件规范的所有权利归Intel公司所有。同时，文档中可能提及的其他名称和品牌可能是其他公司的财产。 AC ‘97规范是个人计算机音频系统设计的关键参考文档，它定义了音频处理和通信的标准接口，为硬件制造商提供了兼容性和互操作性的基础。随着技术的发展，AC ‘97规范的不断更新和完善，确保了音频解决方案能够满足不断变化的市场需求。

AC ‘97 Component Specification Revision 2.3 Rev 1.0

Pin Signal Name Type Description

43 GPIO0 IO Optional Vendor specific GPIO

44 GPIO1 IO Optional Vendor specific GPIO

45 ID0# I Codec ID strap pin (or Generic Cap)

46 ID1# I Codec ID strap pin (or Generic Cap)

47 EAPD O External Amplifier Power Control pin

48 SPDIF_OUT O S/PDIF output (or Vendor specific)

Table 4. Digital I/O Signal Descriptions

2.3.3.1 S/PDIF transmitter pin assignment

S/PDIF capable AC ‘97 2.3 Codecs in the standard 48-pin QFP must use pin 48 to implement the S/PDIF output

signal. The list of pins that are disabled in the ATE test mode should include the S/PDIF output pin.

In addition, it is suggested that the Codec implement a sensing capability that detects S/PDIF output pin 48 strapped

“high” during power up and disables the S/PDIF capability bit in Register 28h. When disabled, the SPSA and

SPCV bits in Register 2Ah, and all bits in the S/PDIF Control Register 3Ah should return “0” when read. This

optional feature allows system designers to populate or depopulate S/PDIF connector hardware, while maintaining

automatic detection in the driver.

2.3.4 Analog I/O

These signals connect the AC ‘97 Codec to analog sources and sinks, including microphones and speakers.

AC ‘97 Component Specification Revision 2.3 Rev 1.0

3. Controller, Codec, and AC-link

This section describes the physical and high-level functional aspects of the AC ‘97 Controller to Codec interface,

referred to as AC-link. For a detailed description of AC-link protocols, slot and bit assignments, refer to Section 4.

3.1 AC-link Physical interface

The AC ‘97 Codec communicates with its companion Digital Controller via the AC-link digital serial interface.

AC-link has been defined to support connections between a single Controller and up to four Codecs. All digital

audio, modem, and handset data streams, as well as all control (command/status) information are communicated

over this serial interconnect, which consists of a clock (BIT_CLK), frame synchronization (SYNC), serial data in

(SDATA_IN), serial data out (SDATA_OUT), and a reset (RESET#).

3.2 Controller to Single Codec

The simplest and most common AC ‘97 system configuration is a point-to-point AC-link connection between

Controller and Codec, as illustrated in Figure 6.

SYNC

BIT_CLK

SDATA_OUT

AC '97 Codec

(Primary)

AC '97 Controller

RESET#

SDATA_IN

Figure 6. Controller to Codec connections

A primary codec may act as either a source or a consumer of the bit clock, depending on the configuration.

While RESET# is asserted, if a clock is present at the BIT_CLK pin for at least five cycles before RESET# is de-

asserted, then the codec is a consumer of BIT_CLK, and must not drive BIT_CLK when RESET# is de-asserted.

The clock is being provided by other than the primary codec, for instance by the controller or an independent clock

chip. In this case the primary codec must act as a consumer of the BIT_CLK signal as if it were a secondary codec.

This clock source detection must be done each time the RESET# line is asserted. In the case of a warm reset, where

the clock is halted but RESET# is not asserted, the codec must remember the clock source, and not begin generating

the clock on the assertion of SYNC if the codec had previously determined that it was a consumer of BIT_CLK.

AC ‘97 Component Specification Revision 2.3 Rev 1.0

AC'97 Clock Source

Detection

RESET# Signal Asserted

BIT_CLK Toggling?

12.288MHz signal on BIT_CLK is

being generated externally; codec

uses this signal as the clock.

Yes

After RESET# Signal

Deasserted

24.576MHz

crystal present?

24.576MHz Crystal on XTL_IN

and XTL_OUT used by codec to

generate clock on BIT_CLK

Yes

24.576MHz

oscillator present?

24.576 MHz signal on XTL_IN

used by codec to generate

12.288MHz clock on BIT_CLK

Yes

14.318MHz

oscillator presnent?

14.318 MHz signal on XTL_IN

used by codec to generate

12.288MHz clock on BIT_CLK

Yes

Error condition - no clock

source present

Figure 7. Codec Clock Source Detection

If, when the RESET# signal has been de-asserted, the codec has not detected a signal on BIT_CLK as defined in the

previous paragraph then the AC ‘97 Codec derives its clock internally from an externally attached 24.576 MHz

crystal

or oscillator, or optionally from an external 14.318MHz oscillator

, and drives a buffered 12.288MHz clock

to its digital companion Controller over AC-link under the signal name “BIT_CLK”. Clock jitter at the DACs and

ADCs is a fundamental impediment to high quality output, and the internally generated clock will provide AC ‘97

with a clean clock that is independent of the physical proximity of AC ‘97’s companion Digital Controller

(henceforth referred to as “the Controller”).

If BIT_CLK begins toggling while the RESET# signal is still asserted, the clock is being provided by other than the

primary codec, for instance by the controller or by a discrete clock source. In this case, the primary codec must act

as a consumer of the BIT_CLK signal as if it were a secondary codec.

This figure is for reference of end states only, and is not intended to imply an actual detection sequence. The

actual flow of the detection is left up to the codec manufacturer.

The use of crystal is recommended, but an external oscillator may also be input to AC ‘97 XTAL_IN

The mechanism used to determine whether a 14.318MHz or other oscillator is attached to the primary codec is not

currently defined, and is left up to each codec manufacturer. This may be specified in the future revisions of this

specification.

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