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首页三星S3C2451 ARM9处理器用户手册
"ARM9 S3C2451用户手册,由Samsung Electronics Co., Ltd于2009年发布,版本1.10,包含了关于16/32位RISC微处理器的详细信息。手册警告可能存在错误或遗漏,并强调Samsung不承担任何由此导致的后果责任。Samsung保留随时改进产品或规格的权利,但不保证更新文档以反映这些变更。此外,购买半导体设备并不意味着获得Samsung或其他公司的专利使用权,且Samsung不对产品的适用性、特定用途的性能或使用任何产品或电路可能产生的责任提供任何保修、陈述或保证。"
**ARM9 S3C2451处理器详解**
ARM9 S3C2451是一款基于RISC(Reduced Instruction Set Computer)架构的微处理器,由Samsung公司设计。RISC架构以其高效能和低功耗著称,广泛应用于嵌入式系统。S3C2451是ARM9系列中的一个成员,它提供了16/32位数据处理能力,适应多种应用场景。
**处理器特性**
1. **高性能核心**:ARM9内核通常具有较高的时钟频率,S3C2451也不例外,能够提供良好的处理速度,适合需要实时处理和复杂计算的应用。
2. **内存管理单元(MMU)**:具备MMU功能,可以支持虚拟地址映射,便于实现多任务操作系统,如Linux等。
3. **接口扩展**:S3C2451通常配备丰富的外设接口,如I2C、SPI、UART、USB、以太网MAC等,方便与各种外围设备连接。
4. **电源管理**:内置电源管理模块,有助于优化功耗,适应电池供电或低功耗应用。
5. **多媒体支持**:可能包括图像处理加速器、音频编解码器等,用于多媒体应用。
**手册内容**
该用户手册会详细解释以下内容:
1. **硬件概述**:介绍处理器的物理结构、引脚定义、电源要求等。
2. **指令集**:列出ARM9指令集,包括数据处理、分支、浮点运算等。
3. **系统控制**:描述如何配置和控制处理器的各种寄存器,以调整其行为。
4. **中断和异常**:详细说明中断和异常处理机制,以及如何设置中断向量。
5. **外设接口**:解释如何与各种外设通信,包括配置和操作方法。
6. **开发和调试**:提供开发工具和调试策略,帮助开发者进行软件开发和问题排查。
7. **应用示例**:可能包含一些基本应用的示例代码,帮助用户快速上手。
8. **安全注意事项**:提醒用户在使用过程中需要注意的安全问题和操作指南。
**法律声明**
手册中的法律声明强调了Samsung对可能存在的错误或遗漏不承担责任,同时指出购买半导体设备不包含对Samsung或其他公司专利权的授权。用户在使用产品时应自行承担风险,Samsung不提供任何明示或暗示的保修。
ARM9 S3C2451用户手册是开发者和工程师理解并有效利用这款处理器的关键参考资料,涵盖了从硬件到软件开发的全方位指导。
xii S3C2451X RISC MICROPROCESSOR
Table of Contents (Continued)
Chapter 20 HS_SPI Controller
1 Overview....................................................................................................................................................20-1
2 Features ....................................................................................................................................................20-1
3 Signal Descriptions....................................................................................................................................20-2
4 Operation...................................................................................................................................................20-2
4.1 Operation Mode ...............................................................................................................................20-3
4.2 FIFO Access ....................................................................................................................................20-3
4.3 Trailing Bytes in the Rx FIFO...........................................................................................................20-3
4.4 Packet Number Control ...................................................................................................................20-3
4.5 NCS Control.....................................................................................................................................20-3
4.6 HS_SPI Transfer Format .................................................................................................................20-4
5 External Loading Capacitance ..................................................................................................................20-5
6 Special Function Register Descriptions ....................................................................................................20-5
6.1 Setting Sequence of Special Function Register ..............................................................................20-5
6.2 Special Function Register................................................................................................................20-6
Chapter 21 SD/MMC Host Controller
1 Overview....................................................................................................................................................21-1
2 Features ....................................................................................................................................................21-1
3 Block Diagram ...........................................................................................................................................21-2
4 Sequence ..................................................................................................................................................21-3
4.1 SD Card Detection Sequence..........................................................................................................21-3
4.2 SD Clock Supply Sequence.............................................................................................................21-4
4.3 SD Clock Stop Sequence ................................................................................................................21-5
4.4 SD Clock Frequency Change Sequence.........................................................................................21-5
4.5 SD Bus Power Control Sequence....................................................................................................21-6
4.6 Change Bus Width Sequence..........................................................................................................21-7
4.7 Timeout Setting for DAT Line ..........................................................................................................21-8
4.8 SD Transaction Generation .............................................................................................................21-8
4.9 SD Command Issue Sequence .......................................................................................................21-9
4.10 Command Complete Sequence.....................................................................................................21-10
4.11 Transaction Control with Data Transfer Using DAT Line ..............................................................21-12
4.12 Abort Transaction...........................................................................................................................21-16
5 SDI Special Registers ...............................................................................................................................21-17
5.1 Configuration Register Types ..........................................................................................................21-17
5.2 SDMA System Address Register.....................................................................................................21-18
5.3 Block Size Register..........................................................................................................................21-19
5.4 Block Count Register .......................................................................................................................21-21
5.5 Argument Register...........................................................................................................................21-22
5.6 Transfer Mode Register...................................................................................................................21-23
5.7 Command Register..........................................................................................................................21-25
5.8 Response Register ..........................................................................................................................21-27
5.9 Buffer Data Port Register.................................................................................................................21-29
5.10 Present State Regis
ter...................................................................................................................21-30
5.11 Host Control Register ....................................................................................................................21-36
5.12 Power Control Register..................................................................................................................21-37
S3C2451X RISC MICROPROCESSOR xiii
Table of Contents (Continued)
Chapter 21 SD/MMC Host Controller (Continued)
5.13 Block Gap Control Register...........................................................................................................21-38
5.14 Wakeup Control Register ..............................................................................................................21-40
5.15 Clock Control Register ..................................................................................................................21-41
5.16 Timeout Control Register ..............................................................................................................21-43
5.17 Software Reset Register ...............................................................................................................21-44
5.18 Normal Interrupt Status Register...................................................................................................21-46
5.19 Error Interrupt Status Register ......................................................................................................21-50
5.20 Normal Interrupt Status Enable Register ......................................................................................21-53
5.21 Error Interrupt Status Enable Register ..........................................................................................21-55
5.22 Normal Interrupt Signal Enable Register.......................................................................................21-56
5.23 Error Interrupt Signal Enable Register .......................................................................................... 21-58
5.24 Autocmd12 Error Status Register..................................................................................................21-59
5.25 Capabilities Register......................................................................................................................21-61
5.26 Maximum Current Capabilities Register........................................................................................21-63
5.27 Control Register 2..........................................................................................................................21-64
5.28 Control Register 3..........................................................................................................................21-67
5.29 Debug Register..............................................................................................................................21-68
5.30 Control Register 4..........................................................................................................................21-68
5.31 Force Event Register for Auto CMD12 Error Status .....................................................................21-69
5.32 Force Event Register for Error Interrupt Status.............................................................................21-70
5.33 ADMA Error Status Register .........................................................................................................21-71
5.34 ADMA System Address Register ..................................................................................................21-73
5.35 HOST Controller Version Register ................................................................................................21-74
Chapter 22 LCD Controller
1 Overview ...................................................................................................................................................22-1
1.1 Features...........................................................................................................................................22-2
2 Functional Description ..............................................................................................................................22-3
2.1 Brief of the sub-block.......................................................................................................................22-3
2.2 Data Flow.........................................................................................................................................22-3
2.3 Interface...........................................................................................................................................22-4
2.4 Overview of the Color Data ............................................................................................................. 22-5
2.5 VD signal Connection......................................................................................................................22-18
2.6 Palette usage...................................................................................................................................22-20
3 Window Blending ......................................................................................................................................22-22
3.1 Overview..........................................................................................................................................22-22
3.2 Blending Diagram/Details................................................................................................................22-23
4 Vtime Controller Operation .......................................................................................................................22-26
4.1 RGB Interface..................................................................................................................................22-26
4.2 I80-System Interface .......................................................................................................................22-26
5 Virtual Display ...........................................................................................................................................22-27
6 RGB Interface I/O .....................................................................................................................................22-28
7 LCD CPU Interface I/O (I80-system I/F)...................................................................................................22-29
8 Programmer’s Model.................................................................................................................................22-31
8.1 Overview..........................................................................................................................................22-31
xiv S3C2451X RISC MICROPROCESSOR
Table of Contents (Continued)
Chapter 23 Camera Interface
1 Overview....................................................................................................................................................23-1
1.1 Features...........................................................................................................................................23-2
2 External Interface ......................................................................................................................................23-2
2.1 Signal Description............................................................................................................................23-2
2.2 Timing Diagram................................................................................................................................23-3
3 External/Internal Connection Guide ..........................................................................................................23-5
4 Camera Interface Operation......................................................................................................................23-5
4.1 Two DMA Ports................................................................................................................................23-5
4.2 CLOCK Domain ...............................................................................................................................23-7
4.3 Frame Memory Hirerarchy...............................................................................................................23-7
4.4 Memory Storing Method ..................................................................................................................23-9
4.5 Timing Diagram for Register Setting................................................................................................23-10
4.6 MSDMA Feature ..............................................................................................................................23-13
5 Software Interface .....................................................................................................................................23-14
6 Camera Interface Special Registers .........................................................................................................23-14
6.1 Source Format Register...................................................................................................................23-14
6.2 Window Option Register ..................................................................................................................23-15
6.3 Global Control Register ...................................................................................................................23-17
6.4 Window Option Register 2...............................................................................................................23-19
6.5 Y1 Start Address Register ...............................................................................................................23-19
6.6 Y2 Start Address Register ...............................................................................................................23-19
6.7 Y3 Start Address Register ...............................................................................................................23-20
6.8 Y4 Start Addres
s Register ...............................................................................................................23-20
6.9 Cb1 Start Address Register.............................................................................................................23-20
6.10 Cb2 Start Address Register...........................................................................................................23-21
6.11 Cb3 Start Address Register...........................................................................................................23-21
6.12 Cb4 Start Address Register...........................................................................................................23-21
6.13 Cr1 Start Address Register............................................................................................................23-21
6.14 Cr2 Start Address Register............................................................................................................23-22
6.15 Cr3 Start Address Register............................................................................................................23-22
6.16 Cr4 Start Address Register............................................................................................................23-22
6.17 Codec Target Format Register ......................................................................................................23-23
6.18 Codec DMA Control Register ........................................................................................................23-25
6.19 Register Setting Guide for Codec Scaler and Preview Scaler ......................................................23-26
6.20 Codec Pre-Scaler Control Register 1 ............................................................................................23-29
6.21 Codec Pre-Scaler Control Register 2 ............................................................................................23-29
6.22 Codec Main-Scaler Control Register.............................................................................................23-30
6.23 Codec DMA Target Area Register.................................................................................................23-30
6.24 Codec Status Register...................................................................................................................23-31
6.25 RGB1 Start Address Register........................................................................................................23-31
6.26 RGB2 Start Address Register........................................................................................................23-32
6.27 RGB3 Start Address Register........................................................................................................23-32
6.28 RGB4 Start Addres
s Register........................................................................................................23-32
6.29 Preview Target Format Register....................................................................................................23-33
6.30 Preview DMA Control Register......................................................................................................23-34
S3C2451X RISC MICROPROCESSOR xv
Table of Contents (Continued)
Chapter 23 Camera Interface (Continued)
6.31 Preview Pre-Scaler Control Register 1 .........................................................................................23-35
6.32 Preview Pre-Scaler Control Register 2 .........................................................................................23-35
6.33 Preview Main-Scaler Control Register ..........................................................................................23-36
6.34 Preview DMA Target Area Register ..............................................................................................23-36
6.35 Preview Status Register ................................................................................................................23-37
6.36 Image Capture Enable Register....................................................................................................23-38
6.37 Codec Capture Sequence Register ..............................................................................................23-39
6.38 Codec Scan Line Offset Register..................................................................................................23-40
6.39 Preview Scan Line Offset Register................................................................................................23-40
6.40 Image Effects Register ..................................................................................................................23-42
6.41 MSDMA Y start Address Register.................................................................................................23-43
6.42 MSDMA Cb start Address Register...............................................................................................23-43
6.43 MSDMA Cr start Address Register................................................................................................23-43
6.44 MSDMA Y end Address Register..................................................................................................23-44
6.45 MSDMA Cb end Address Register................................................................................................23-44
6.46 MSDMA Cr end Address Register.................................................................................................23-44
6.47 MSDMA Y Offset Register.............................................................................................................23-45
6.48 MSDMA Cb Offset Register ..........................................................................................................23-45
6.49 MSDMA Cr Offset Register ...........................................................................................................23-45
6.50 MSDMA Source Image Width Register.........................................................................................23-45
6.51 MSDMA Control Register ..............................................................................................................23-47
Chapter 24 ADC & Touch Screen Interface
1 Overview ...................................................................................................................................................24-1
1.1 Features...........................................................................................................................................24-1
2 ADC & Touch Screen Interface Operation................................................................................................24-2
2.1 Block Diagram .................................................................................................................................24-2
2.2 Function Descriptions......................................................................................................................24-3
3 ADC and Touch Screen Interface Special Registers................................................................................24-5
3.1 ADC Control (ADCCON) Register...................................................................................................24-5
3.2 ADC Touch Screen Control (ADCTSC) Register............................................................................24-6
3.3 ADC Start Delay (ADCDLY) Register..............................................................................................24-7
3.4 ADC Conversion Data (ADCDAT0) Register ..................................................................................24-8
3.5 ADC Conversion Data (ADCDAT1) Register ..................................................................................24-9
3.6 ADC Touch Screen up-Down Int Check Register (ADCUPDN)......................................................24-9
3.7 ADC Channel Mux Register (ADCMUX) .........................................................................................24-10
xvi S3C2451X RISC MICROPROCESSOR
Table of Contents (Continued)
Chapter 25 IIS-Bus Interface
1 Overview....................................................................................................................................................25-1
2 Feature ......................................................................................................................................................25-1
3 Signals.......................................................................................................................................................25-1
4 Block Diagram ...........................................................................................................................................25-2
5 Functional Descriptions.............................................................................................................................25-2
5.1 Master/Slave Mode..........................................................................................................................25-3
6 Audio Serial Data Format..........................................................................................................................25-5
6.1 IIS-bus Format .................................................................................................................................25-5
6.2 MSB (Left) Justified..........................................................................................................................25-5
6.3 LSB (Right) Justified ........................................................................................................................25-5
6.4 Sampling Frequency and Master Clock...........................................................................................25-7
6.5 IIS Clock Mapping Table..................................................................................................................25-7
7 Programming guiyde .................................................................................................................................25-8
7.1 Initialization ......................................................................................................................................25-8
7.2 Play Mode (TX mode) with DMA .....................................................................................................25-8
7.3 Recording Mode (RX mode) with DMA ...........................................................................................25-8
7.4 Example Code .................................................................................................................................25-9
8 IIS-BUS Interface Special Registers .........................................................................................................25-15
8.1 IIS Control Register (IISCON)..........................................................................................................25-16
8.2 IIS Mode Register (IISMOD)............................................................................................................25-18
8.3 IIS FIFO Control Register (IISFIC)...................................................................................................25-20
8.4 IIS Prescaler Control Register (IISPSR)..........................................................................................25-20
8.5 IIS Trans
mit Register (IISTXD)........................................................................................................25-21
8.6 IIS Receive Register (IISRXD).........................................................................................................25-21
Chapter 26 IIS Multi Audio Interface
1 Overview....................................................................................................................................................26-1
2 Feature ......................................................................................................................................................26-1
3 Signals.......................................................................................................................................................26-1
4 Block Diagram ...........................................................................................................................................26-2
5 Functional Descriptions.............................................................................................................................26-2
5.1 Master/Slave Mode..........................................................................................................................26-3
5.2 DMA Transfer...................................................................................................................................26-4
6 Audio Serial Data Format..........................................................................................................................26-5
6.1 IIS-Bus Format.................................................................................................................................26-5
6.2 MSB (Left) Justified..........................................................................................................................26-5
6.3 LSB (Right) Justified ........................................................................................................................26-5
6.4 Sampling Frequency and Master Clock...........................................................................................26-7
6.5 IIS Clock Mapping Table..................................................................................................................26-7
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