低电压DDR3 SDRAM手册：MT41K系列详解

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本资源是镁光公司出品的DDR3 SDRAM用户手册，专为需要利用此类高速存储器的用户提供详尽的技术指南。手册主要针对的是低电压版本的DDR3 SDRAM，型号包括MT41K512M4（64MB x 4 x 8 banks）、MT41K256M8（32MB x 8 x 8 banks）以及MT41K128M16（16MB x 16 x 8 banks），这些内存条工作电压为1.35V（兼容1.5V），旨在提供更低的功耗和能耗。以下是一些关键特性： 1. **低电压设计**：DDR3L SDRAM采用1.35V工作电压（1.283V 至 1.45V），相比标准的1.5V DDR3 SDRAM，它具有更低的电压要求，有利于在节能应用中使用。 2. **兼容性**：设备能够向下兼容1.5V DDR3 SDRAM，即在1.5V±0.075V电压范围内仍能正常运行。 3. **接口特性**：支持差分双向数据信号（Data Strobe）和差分时钟输入（CK, CK#），提供了8个内部银行，便于高效的数据传输。 4. **内存管理**：具备可编程的CAS（读取）延迟时间（CL）、POSTED CAS附加延迟（AL）以及写入CAS延迟（CWL）。固定的突发长度（BL）为8，可变突发切片（BC）为4，通过模式寄存器集（MRS）进行设置。 5. **动态功能**：支持在运行过程中动态调整BC4或BL8，以及自刷新模式，以适应不同的应用场景需求。 6. **温度控制**：内存工作范围宽广，从0°C到+95°C，不同温度下有相应的刷新周期（0°C至+85°C为64ms，+85°C至+95°C为32ms）。还包含自刷新温度（SRT）和自动自刷新（ASR）功能。 7. **性能优化**：内置写平滑技术，以及多功能寄存器，有助于提高数据一致性。输出驱动器校准选项保证了信号质量。 8. **标记选择**：手册列出了可供选择的配置类型，如512M4表示512兆字节每组的配置。此手册为工程师、系统设计师以及维护人员提供了关于如何充分利用DDR3L SDRAM的全面信息，包括硬件选型、操作指导和故障排除参考，确保了系统的稳定运行和高性能表现。

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 Ball Assignments (Top View)

1234 67895

DDQ

SSQ

REFDQ

ODT

SSQ

DQ2

NF, DQ6

DDQ

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

NF, DQ7

CK#

A10/AP

A12/BC#

A11

A14

DDQ

SSQ

DDQ

CKE

SSQ

DQ3

NF, DQ5

REFCA

BA1

Notes:

1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef83ed2952

2Gb_DDR3L.pdf - Rev. K 9/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[14:13],

A12/BC#, A11,

A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-

cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-

ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-

vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active

power-down (row active in any bank). CKE is synchronous for power-down entry and exit

and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-

ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-

cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-

nal rank selection on systems with multiple ranks. CS# is considered part of the command

code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with the input data during a write access. Although the DM

ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM

is referenced to V

REFDQ

. DM has an optional use as TDQS on the x8 device.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the

x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the

LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

DDQ

and DC LOW ≤

0.2 × V

DDQ

. RESET# assertion and deassertion are asynchronous.

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-

enced to V

REFDQ

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef83ed2952

2Gb_DDR3L.pdf - Rev. K 9/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A13, A12/BC#,

A11, A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (LDQS, LDQS#, UDQS, UDQS#) is referenced to the crossings of CK and

CK#.