16
6221D–ATARM–12-Mar-07
AT91SAM9260 Preliminary
6.6 Shutdown Logic Pins
The SHDN pin is an output only, which is driven by the Shutdown Controller.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
6.7 Slow Clock Selection
The AT91SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or
the on-chip RC oscillator.
Table 6-1 defines the states for OSCSEL signal.
The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The
32,768 Hz startup delay is 1200 ms whereas it is 200 µs for the internal RC oscillator (refer to
Table 6-1). The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the
device.
7. Processor and Architecture
7.1 ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction
Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
• 8-Kbyte Data Cache, 8-Kbyte Instruction Cache
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
• Write Buffer
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
Table 6-1. Slow Clock Selection
OSCSEL Slow Clock Startup Time
0 Internal RC 240 µs
1 External 32768 Hz 1200 ms
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