I2C总线规格与用户手册

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"UM10204 I2C-busspecificationandusermanual Rev.03—19June2007" I2C（Inter-Integrated Circuit）总线规范和用户手册是针对Philips Semiconductors（现为NXPSemiconductors）开发的一种高效能的双向两线制总线协议的详细指南。该总线设计用于实现集成电路间的高效通信，只需要两条线：串行数据线（SDA）和串行时钟线（SCL）。I2C总线支持串行、8位定向的双向数据传输，具有不同的工作模式以适应不同速度的需求。 1. **标准模式（Standard-mode）**：在标准模式下，I2C总线的数据传输速率可以达到100千比特/秒（kbit/s），适合于低功耗和对速度要求不高的应用。 2. **快速模式（Fast-mode）**：快速模式将数据传输速率提升至400kbit/s，提高了通信效率，适用于许多嵌入式系统和消费电子设备。 3. **快速模式Plus（Fast-mode Plus, Fm+）**：进一步提升传输速度，可达1兆比特/秒（Mbit/s），为需要更快传输速率但又无法采用高速模式的应用提供了选择。 4. **高速模式（High-speed mode）**：最高可达3.4Mbit/s，这种模式适用于需要极高传输速度的场合，如现代的高速数据交换和处理。 I2C总线的这些模式使得它能够在各种不同的应用场景中找到用武之地，从小型嵌入式系统到复杂的多芯片模块。由于其简单性和灵活性，I2C已成为微控制器和其他数字组件之间通信的标准接口。文档还包含了关键词，如I2C、I2C总线、标准模式、快速模式、快速模式Plus、高速模式等，这些都是与I2C技术相关的术语。此外，用户可以通过访问NXPSemiconductors的官方网站或发送电子邮件至指定地址获取更多相关信息。文档修订历史显示，此版本为Rev.03，更新日期为2007年6月19日，表明I2C总线规范随时间不断进行更新和改进以适应技术的发展。 I2C总线是一种强大的通信协议，具有多种速度模式以满足不同需求，且随着技术的进步，其规格也在不断演进。对于任何涉及集成电路间通信的设计者和开发者来说，理解并掌握I2C总线规范至关重要。

User manual Rev. 03 — 19 June 2007 9 of 50

NXP Semiconductors

UM10204

C-bus specification and user manual

3.2 SDA and SCL logic levels

Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be

connected to the I

C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed

and depend on the associated level of V

. Input reference levels are set as 30 % and

70 % of V

; V

is 0.3V

and V

is 0.7V

. See Figure 27, timing diagram. Some

legacy device input levels were fixed at V

= 1.5 V and V

= 3.0 V, but all new devices

require this 30 %/70 % specification. See Section 6

for electrical specifications.

3.3 Data validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH

or LOW state of the data line can only change when the clock signal on the SCL line is

LOW (see Figure 4

). One clock pulse is generated for each data bit transferred.

3.4 START and STOP conditions

All transactions begin with a START (S) and can be terminated by a STOP (P) (see

Figure 5

). A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START

condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP

condition.

START and STOP conditions are always generated by the master. The bus is considered

to be busy after the START condition. The bus is considered to be free again a certain

time after the STOP condition. This bus free situation is specified in Section 6

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In

this respect, the START (S) and repeated START (Sr) conditions are functionally identical.

For the remainder of this document, therefore, the S symbol will be used as a generic term

to represent both the START and repeated START conditions, unless Sr is particularly

relevant.

Fig 4. Bit transfer on the I

C-bus

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 5. START and STOP conditions

mba608

SDA

SCL

STOP condition

SDA

SCL

START condition

User manual Rev. 03 — 19 June 2007 10 of 50

NXP Semiconductors

UM10204

C-bus specification and user manual

Detection of START and STOP conditions by devices connected to the bus is easy if they

incorporate the necessary interfacing hardware. However, microcontrollers with no such

interface have to sample the SDA line at least twice per clock period to sense the

transition.

3.5 Byte format

Every byte put on the SDA line must be 8 bits long. The number of bytes that can be

transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge

bit. Data is transferred with the Most Significant Bit (MSB) first (see Figure 6

). If a slave

cannot receive or transmit another complete byte of data until it has performed some other

function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to

force the master into a wait state. Data transfer then continues when the slave is ready for

another byte of data and releases clock line SCL.

3.6 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to

signal the transmitter that the byte was successfully received and another byte may be

sent. All clock pulses including the acknowledge 9

clock pulse are generated by the

master.

The Acknowledge signal is defined as follows: the transmitter releases the SDA line

during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it

remains stable LOW during the HIGH period of this clock pulse (see Figure 4

). Set-up and

hold times (specified in Section 6

) must also be taken into account.

When SDA remains HIGH during this 9

clock pulse, this is defined as the Not

Acknowledge signal. The master can then generate either a STOP condition to abort the

transfer, or a repeated START condition to start a new transfer. There are five conditions

that lead to the generation of a NACK:

1. No receiver is present on the bus with the transmitted address so there is no device to

respond with an acknowledge.

2. The receiver is unable to receive or transmit because it’s performing some real-time

function and is not ready to start communication with the master.

3. During the transfer the receiver gets data or commands that it does not understand.

4. During the transfer, the receiver cannot receive any more data bytes.

5. A master-receiver needs to signal the end of the transfer to the slave transmitter.

Fig 6. Data transfer on the I

C-bus

S or Sr Sr or P

SDA

SCL

MSB

1 2 7 8 9 1 2 3 to 8 9

ACK ACK

002aac861

START or

repeated START

condition

STOP or

repeated START

condition

acknowledgement

signal from slave

byte complete,

interrupt within slave

clock line held LOW

while interrupts are serviced

acknowledgement

signal from receiver

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