I2C总线3V与5V设备通信转换指南

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"IIC(Inter-Integrated Circuit)是一种由飞利浦半导体(现NXP Semiconductors)开发的两线式串行接口，常用于低速、短距离通信，如连接微控制器与各种外围设备。这个资料主要讨论如何在3V和5V的IIC器件之间进行转换，以实现不同电压等级的单片机之间的通信。" IIC总线协议自1982年发布以来，经历了多个版本的更新，包括1.0、2.0和2.1版本，以适应不断变化的电子设计需求。该协议具有许多对设计师和制造商有益的特点，如简化硬件设计、减少引脚数量、降低系统成本，并且允许多设备在同一总线上通信。 IIC总线的基本概念是采用两条线——数据线SDA（Serial Data）和时钟线SCL（Serial Clock）进行通信。其一般特性包括数据有效性、起始和停止条件、数据传输格式以及仲裁和时钟生成机制。在数据传输过程中，数据的有效性依赖于时钟信号，起始和停止条件用于标记数据传输的开始和结束。每个数据字节由8位组成，接收方通过发送一个应答位（ACK）来确认接收到的数据。在IIC总线中，数据传输的仲裁是在不中断当前传输的情况下，确保只有一个设备发送数据。同步机制则确保所有设备的时钟信号同步，以避免数据错误。7位地址格式是标准的地址模式，其中定义了不同的比特位，包括通用呼叫地址、起始字节和兼容其他总线的CBUS格式。为了扩展标准模式的IIC总线，有两个高速模式：Fast Mode和High Speed (Hs-) Mode。Fast Mode支持最高1MHz的数据传输速率，而Hs-Mode则进一步提升了速度，可达到3.4MHz以上的高速传输，适合需要快速通信的应用。 IIC 3V与5V器件转换涉及到的关键知识点包括： 1. IIC总线协议的基本原理和历史版本。 2. 数据传输的规则，如起始和停止条件、数据有效性、应答机制。 3. 总线仲裁和时钟同步机制。 4. 7位地址格式及其不同应用。 5. IIC的高速模式，如Fast Mode和Hs-Mode，以及它们对数据传输速率的提升。理解这些知识点对于实现3V和5V单片机之间的IIC通信至关重要，这通常需要使用到电平转换器或适当的接口电路，以确保信号在不同电压级别间的正确传输。

Philips Semiconductors

The I

C-bus specification

Generation of clock signals on the I

C-bus is always the

responsibility of master devices; each master generates its

own clock signals when transferring data on the bus. Bus

clock signals from a master can only be altered when they

are stretched by a slow-slave device holding-down the

clock line, or by another master when arbitration occurs.

5 GENERAL CHARACTERISTICS

Both SDA and SCL are bi-directional lines, connected to a

positive supply voltage via a current-source or pull-up

resistor (see Fig.3). When the bus is free, both lines are

HIGH. The output stages of devices connected to the bus

must have an open-drain or open-collector to perform the

wired-AND function. Data on the I

C-bus can be

transferred at rates of up to 100 kbit/s in the

Standard-mode, up to 400 kbit/s in the Fast-mode, or up to

3.4 Mbit/s in the High-speed mode. The number of

interfaces connected to the bus is solely dependent on the

bus capacitance limit of 400 pF. For information on

High-speed mode master devices, see Section 13.

6 BIT TRANSFER

Due to the variety of different technology devices (CMOS,

NMOS, bipolar) which can be connected to the I

C-bus,

the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not

fixed and depend on the associated level of V

(see

Section 15 for electrical specifications). One clock pulse is

generated for each data bit transferred.

6.1 Data validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is

LOW (see Fig.4).

Fig.3 Connection of Standard- and Fast-mode devices to the I

C-bus.

MBC631

SCLKN1

OUT

SCLK

DATAN1

OUT

DATA

DEVICE 1

SDA (Serial Data Line)

SCL (Serial Clock Line)

SCLKN2

OUT

SCLK

DATAN2

OUT

DATA

DEVICE 2

pull-up

resistors

Philips Semiconductors

The I

C-bus specification

7 TRANSFERRING DATA

7.1 Byte format

Every byte put on the SDA line must be 8-bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most

significant bit (MSB) first (see Fig.6). If a slave can’t

receive or transmit another complete byte of data until it

has performed some other function, for example servicing

an internal interrupt, it can hold the clock line SCL LOW to

force the master into a wait state. Data transfer then

continues when the slave is ready for another byte of data

and releases clock line SCL.

In some cases, it’s permitted to use a different format from

the I

C-bus format (for CBUS compatible devices for

example). A message which starts with such an address

can be terminated by generation of a STOP condition,

even during the transmission of a byte. In this case, no

acknowledge is generated (see Section 10.1.3).

7.2 Acknowledge

Data transfer with acknowledge is obligatory. The

acknowledge-related clock pulse is generated by the

master. The transmitter releases the SDA line (HIGH)

during the acknowledge clock pulse.

The receiver must pull down the SDA line during the

acknowledge clock pulse so that it remains stable LOW

during the HIGH period of this clock pulse (see Fig.7). Of

course, set-up and hold times (specified in Section 15)

must also be taken into account.

Usually, a receiver which has been addressed is obliged to

generate an acknowledge after each byte has been

received, except when the message starts with a CBUS

address (see Section 10.1.3).

When a slave doesn’t acknowledge the slave address (for

example, it’s unable to receive or transmit because it’s

performing some real-time function), the data line must be

left HIGH by the slave. The master can then generate

either a STOP condition to abort the transfer, or a repeated

START condition to start a new transfer.

If a slave-receiver does acknowledge the slave address

but, some time later in the transfer cannot receive any

more data bytes, the master must again abort the transfer.

This is indicated by the slave generating the

not-acknowledge on the first byte to follow. The slave

leaves the data line HIGH and the master generates a

STOP or a repeated START condition.

If a master-receiver is involved in a transfer, it must signal

the end of data to the slave- transmitter by not generating

an acknowledge on the last byte that was clocked out of

the slave. The slave-transmitter must release the data line

to allow the master to generate a STOP or repeated

START condition.

Fig.6 Data transfer on the I

C-bus.

handbook, full pagewidth

MSC608

SDA

SCL

STOP or

repeated START

condition

START or

repeated START

condition

1 2 3 - 8 9

ACK

7812

MSB

acknowledgement

signal from slave

byte complete,

interrupt within slave

clock line held low while

interrupts are serviced

acknowledgement

signal from receiver

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