88E6095：详解8FE+3GE堆叠以太网交换机的QoS与802.1Q技术
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更新于2024-07-27
收藏 3.26MB PDF 举报 88E6095是一款高性能的LinkStreet系列以太网交换机，它集成了8个10/100/1000Mbps的Fast Ethernet端口（8FE）和3个10/100Mbps的吉比特以太网端口（3GE），支持堆叠功能，能够提供更高的带宽和扩展性。该交换机的核心特性在于其内置的Quality of Service (QoS) 功能，允许用户对网络流量进行优先级管理和控制，确保关键业务应用得到优先处理，提升网络效率和稳定性。
此外，88E6095支持802.1Q标准，这是一种用于标记以太网帧的协议，使得交换机可以基于VLAN（虚拟局域网）对数据包进行管理，增强了网络的安全性和隔离能力。该产品的设计文档MV-S102629-00Rev.C是在2006年6月发布的，强调了版权保护，所有复制或传播行为必须得到Marvell公司的明确书面许可。
Marvell公司对于本产品提供的信息不承担任何明示或暗示的保证，包括关于适销性和特定用途的保证。同时，明确指出该产品并非设计用于涉及生命支持系统或可能导致严重后果的应用环境，用户在使用时需谨慎考虑。
88E6095以太网交换机是专为商业网络环境设计的，它结合了高带宽、QoS控制和VLAN支持，旨在满足企业级网络对性能、安全性和可管理性的需求。然而，用户在使用时应遵循产品手册中的警告和限制，并确保在适宜的环境下操作，以避免潜在的风险。
Doc. No. MV-S102629-00 Rev. C
CONFIDENTIAL
Copyright © 2006 Marvell
Page 16 Document Classification: Proprietary Information June 9, 2006, Advance
Link Street
®
88E6092/88E6095/88E6095F
8 FE + 3 GE Stackable Ethernet Switch with QoS and 802.1Q
List of Figures
Figure 1: 88E6092/88E6095 Device 176 TQFP EPAD Package Pinout............................................................ 18
Figure 2: 88E6095F Device 216 LQFP EPAD Package Pinout ......................................................................... 19
Figure 3: 16 FE + 2 GE Ports............................................................................................................................. 56
Figure 4: 24 FE + 2 GE with 88E6095 X 3......................................................................................................... 57
Figure 5: 48 FE + 4 GE wit 88E6095 X 6 + 88E6185 ........................................................................................ 58
Figure 6: Fiber to the Curb................................................................................................................................. 59
Figure 7: SOHO/SMB Router with FE and GE Ports ......................................................................................... 59
Figure 8: MII MAC Interface Pins ....................................................................................................................... 64
Figure 9: MII PHY Interface Pins........................................................................................................................ 65
Figure 10: GMII MAC Interface Pins .................................................................................................................... 66
Figure 11: GMII PHY Interface Pins..................................................................................................................... 67
Figure 12: Switch Data Flow ................................................................................................................................ 69
Figure 13: Format of an ATU Entry ...................................................................................................................... 86
Figure 14: Switch Operation with VLANs Disabled .............................................................................................. 94
Figure 15: Switch Operation with a Typical Router VLAN Configuration .............................................................95
Figure 16: Switch Operation with another Example VLAN Configuration ............................................................ 96
Figure 17: Format of a VTU Entry...................................................................................................................... 100
Figure 18: IEEE Tag Frame Format................................................................................................................... 105
Figure 19: IPv4 Priority Frame Format............................................................................................................... 108
Figure 20: IPv6 Priority Frame Format............................................................................................................... 108
Figure 21: IPv4 IGMP Snoop Format................................................................................................................. 109
Figure 22: IPv6 MLD Snoop Format .................................................................................................................. 110
Figure 23: Ingress Forward Tag Format ............................................................................................................ 112
Figure 24: Ingress From_CPU Tag Format........................................................................................................ 113
Figure 25: Ingress Header Format ..................................................................................................................... 116
Figure 26: Double Tag Format........................................................................................................................... 117
Figure 27: Switch Queues.................................................................................................................................. 120
Figure 28: IEEE Tag Frame Format................................................................................................................... 124
Figure 29: Double Tag Format........................................................................................................................... 125
Figure 30: Egress Forward Tag Format ............................................................................................................. 128
Figure 31: Egress To_CPU Tag Format ........................................................................................................... 129
Figure 32: Egress Header Format...................................................................................................................... 131
Figure 33: Device Transmit Block Diagram........................................................................................................ 136
Figure 34: Device Receive Block Diagram......................................................................................................... 137
Figure 35: Line Loopback Data Path.................................................................................................................. 151
Figure 36: Possible Solutions for Case One ...................................................................................................... 155
Figure 37: Possible Solutions for Case Two ...................................................................................................... 156
Figure 38: Serial LEDENA High Clocking with COLX in Dual Mode, Error Off, and DUPLEX in Single Mode.. 157
Figure 39: Serial LED Conversion...................................................................................................................... 158
Figure 40: Typical MDC/MDIO Read Operation................................................................................................. 162
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