Marvell 88E6095堆叠以太网交换机数据手册：QoS与802.1Q特性
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收藏 3.26MB PDF 举报 88E6095芯片数据手册是一份详细介绍LinkStreet品牌的高性能堆叠以太网交换机的文档，该产品型号支持8FE（八个千兆以太网端口）和3GE（三个十兆以太网端口）。这是一款具备服务质量(QoS)和802.1Q标准功能的交换机，旨在满足企业级网络环境中对带宽管理、可靠性和性能的需求。
这份数据手册的版本为MV-S102629-00 Rev.C，发布日期为2006年6月9日。Marvell作为制造商，明确指出此文档不得未经其书面许可进行任何形式的复制或传输，包括但不限于电子或机械复制，无论是出于何种目的。Marvell保留随时更新文档的权利，而无需通知用户，并且声明对此文档中的所有信息、文本、图形和其他内容不提供任何形式的明示或默示保证，包括但不限于商品适销性或特定用途的适用性。
特别值得注意的是，88E6095芯片并不是为生命支持设备或可能导致严重后果的应用设计的，因此在使用时必须确保符合安全规范。对于文中所描述的产品，用户或接收者在没有适当美国联邦通信委员会(FCC)认证的情况下，不应将其用于这类特殊应用场景。
88E6095芯片数据手册提供了交换机的技术规格、功能特性、操作指南以及重要的安全注意事项，是工程师、系统集成商和技术支持人员进行产品选型、配置和维护的重要参考资源。了解并遵循其中的规定，能确保设备的正确使用和最大化性能发挥。
Doc. No. MV-S102629-00 Rev. C
CONFIDENTIAL
Copyright © 2006 Marvell
Page 16 Document Classification: Proprietary Information June 9, 2006, Advance
Link Street
®
88E6092/88E6095/88E6095F
8 FE + 3 GE Stackable Ethernet Switch with QoS and 802.1Q
List of Figures
Figure 1: 88E6092/88E6095 Device 176 TQFP EPAD Package Pinout............................................................ 18
Figure 2: 88E6095F Device 216 LQFP EPAD Package Pinout ......................................................................... 19
Figure 3: 16 FE + 2 GE Ports............................................................................................................................. 56
Figure 4: 24 FE + 2 GE with 88E6095 X 3......................................................................................................... 57
Figure 5: 48 FE + 4 GE wit 88E6095 X 6 + 88E6185 ........................................................................................ 58
Figure 6: Fiber to the Curb................................................................................................................................. 59
Figure 7: SOHO/SMB Router with FE and GE Ports ......................................................................................... 59
Figure 8: MII MAC Interface Pins ....................................................................................................................... 64
Figure 9: MII PHY Interface Pins........................................................................................................................ 65
Figure 10: GMII MAC Interface Pins .................................................................................................................... 66
Figure 11: GMII PHY Interface Pins..................................................................................................................... 67
Figure 12: Switch Data Flow ................................................................................................................................ 69
Figure 13: Format of an ATU Entry ...................................................................................................................... 86
Figure 14: Switch Operation with VLANs Disabled .............................................................................................. 94
Figure 15: Switch Operation with a Typical Router VLAN Configuration .............................................................95
Figure 16: Switch Operation with another Example VLAN Configuration ............................................................ 96
Figure 17: Format of a VTU Entry...................................................................................................................... 100
Figure 18: IEEE Tag Frame Format................................................................................................................... 105
Figure 19: IPv4 Priority Frame Format............................................................................................................... 108
Figure 20: IPv6 Priority Frame Format............................................................................................................... 108
Figure 21: IPv4 IGMP Snoop Format................................................................................................................. 109
Figure 22: IPv6 MLD Snoop Format .................................................................................................................. 110
Figure 23: Ingress Forward Tag Format ............................................................................................................ 112
Figure 24: Ingress From_CPU Tag Format........................................................................................................ 113
Figure 25: Ingress Header Format ..................................................................................................................... 116
Figure 26: Double Tag Format........................................................................................................................... 117
Figure 27: Switch Queues.................................................................................................................................. 120
Figure 28: IEEE Tag Frame Format................................................................................................................... 124
Figure 29: Double Tag Format........................................................................................................................... 125
Figure 30: Egress Forward Tag Format ............................................................................................................. 128
Figure 31: Egress To_CPU Tag Format ........................................................................................................... 129
Figure 32: Egress Header Format...................................................................................................................... 131
Figure 33: Device Transmit Block Diagram........................................................................................................ 136
Figure 34: Device Receive Block Diagram......................................................................................................... 137
Figure 35: Line Loopback Data Path.................................................................................................................. 151
Figure 36: Possible Solutions for Case One ...................................................................................................... 155
Figure 37: Possible Solutions for Case Two ...................................................................................................... 156
Figure 38: Serial LEDENA High Clocking with COLX in Dual Mode, Error Off, and DUPLEX in Single Mode.. 157
Figure 39: Serial LED Conversion...................................................................................................................... 158
Figure 40: Typical MDC/MDIO Read Operation................................................................................................. 162
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