ARMv8-A A32/T32指令集架构详解：beta版用户指南

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ARMv8-A A32/T32指令集架构参考手册（DDI0597）是Arm公司于2010年至2019年期间发布的版权作品，适用于ARMv8-A架构。这份文档详细介绍了ARMv8架构下的A32和T32指令集，这两个指令集在64位架构中扮演着核心角色，尤其是对于那些追求高性能和低功耗的应用场景。 A32（32-bit ARM Architecture）指令集是针对32位应用程序设计的，它提供了兼容性和向后兼容性，使现有的32位软件能够在新的硬件平台上运行。这包括了对ARMv7指令集的扩展，旨在提高性能和效率，比如增加了向量处理、内存访问优化以及对多媒体处理的支持。而T32（ Thumb-32）指令集则是在Thumb-2的基础上发展而来，提供了一种更轻量级的指令集，以节省代码空间和提升执行速度。T32特别适合于嵌入式系统和低功耗设备，因为它能以较小的代码体积实现较高的执行效率。手册中提到的"Armv8, for Armv8-A architecture profile"部分着重于与ARMv8架构的集成，这是ARMv8-A架构的一个关键特性，它不仅支持传统的A32指令集，还引入了64位操作，增强了系统性能和扩展性。此外，手册提到了该版本的非保密性质（Non-Confidential-Beta），意味着其中包含的信息可供开发者广泛使用，但需遵守版权和专利规定，未经许可不得复制或实施。值得注意的是，手册还提供了关于此版本变更历史和已知问题的参考资料链接，即A32/T32 ISAXML for Armv8.5 (00bet10)中的Release Notes，这对于开发者在实际应用中理解和解决可能出现的问题至关重要。 ARMv8-A A32/T32指令集架构参考手册是开发人员深入理解ARMv8-A架构及其指令集特性的必备资源，它涵盖了从基础原理到实践应用的广泛内容，确保了软件和硬件之间的高效协作。

• Inside an IT block, if ADC<c> <Rd>, <Rn>, <Rd> has <Rd> and <Rn> both in the range R0-R7, it is assembled using encoding T1 as

though ADC<c> <Rd>, <Rn> had been written.

To prevent either of these happening, use the .W qualifier.

Operation

if ConditionPassed() then

EncodingSpecificOperations();

shifted = Shift(R[m], shift_t, shift_n, PSTATE.C);

(result, nzcv) = AddWithCarry(R[n], shifted, PSTATE.C);

if d == 15 then // Can only occur for A32 encoding

if setflags then

ALUExceptionReturn(result);

else

ALUWritePC(result);

else

R[d] = result;

if setflags then

PSTATE.<N,Z,C,V> = nzcv;

Operational information

If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:

• The execution time of this instruction is independent of:

◦ The values of the data supplied in any of its registers.

◦ The values of the NZCV flags.

• The response of this instruction to asynchronous exceptions does not vary based on:

◦ The values of the data supplied in any of its registers.

◦ The values of the NZCV flags.

Internal version only: isa v00_96, pseudocode r8p5_00bet2_rc5 ; Build timestamp: 2019-03-28T07:59

ADC, ADCS (register) Page 15

ADC, ADCS (register-shifted register)

Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the

destination register, and can optionally update the condition flags based on the result.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

!= 1111 0 0 0 0 1 0 1 S Rn Rd Rs 0 stype 1 Rm

cond

Flag setting (S == 1)

ADCS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs>

Not flag setting (S == 0)

ADC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs>

d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs);

setflags = (S == '1'); shift_t = DecodeRegShift(stype);

if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;

For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c> See Standard assembler syntax fields.

<q> See Standard assembler syntax fields.

<Rd> Is the general-purpose destination register, encoded in the "Rd" field.

<Rn> Is the first general-purpose source register, encoded in the "Rn" field.

<Rm> Is the second general-purpose source register, encoded in the "Rm" field.

<shift> Is the type of shift to be applied to the second source register, encoded in “stype”:

stype <shift>

00 LSL

01 LSR

10 ASR

11 ROR

<Rs> Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.

Operation

if ConditionPassed() then

EncodingSpecificOperations();

shift_n = UInt(R[s]<7:0>);

shifted = Shift(R[m], shift_t, shift_n, PSTATE.C);

(result, nzcv) = AddWithCarry(R[n], shifted, PSTATE.C);

R[d] = result;

if setflags then

PSTATE.<N,Z,C,V> = nzcv;

Operational information

If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:

• The execution time of this instruction is independent of:

◦ The values of the data supplied in any of its registers.

◦ The values of the NZCV flags.

ADC, ADCS (register-shifted

Page 16

ADD<c>{<q>} <Rdn>, #<imm8> // (Inside IT block, and <Rdn>, <imm8> can be represented in T1)

ADD<c>{<q>} {<Rdn>,} <Rdn>, #<imm8> // (Inside IT block, and <Rdn>, <imm8> cannot be represented in T1)

ADDS{<q>} <Rdn>, #<imm8> // (Outside IT block, and <Rdn>, <imm8> can be represented in T1)

ADDS{<q>} {<Rdn>,} <Rdn>, #<imm8> // (Outside IT block, and <Rdn>, <imm8> cannot be represented in T1)

d = UInt(Rdn); n = UInt(Rdn); setflags = !InITBlock(); imm32 = ZeroExtend(imm8, 32);

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 1 0 i 0 1 0 0 0 S != 1101 0 imm3 Rd imm8

ADD (S == 0)

ADD<c>.W {<Rd>,} <Rn>, #<const> // (Inside IT block, and <Rd>, <Rn>, <const> can be represented in T1 or T2)

ADD{<c>}{<q>} {<Rd>,} <Rn>, #<const>

ADDS (S == 1 && Rd != 1111)

ADDS.W {<Rd>,} <Rn>, #<const> // (Outside IT block, and <Rd>, <Rn>, <const> can be represented in T1 or T2)

ADDS{<c>}{<q>} {<Rd>,} <Rn>, #<const>

if Rd == '1111' && S == '1' then SEE "CMN (immediate)";

if Rn == '1101' then SEE "ADD (SP plus immediate)";

d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 = T32ExpandImm(i:imm3:imm8);

if (d == 15 && !setflags) || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 1 0 i 1 0 0 0 0 0 != 11x1 0 imm3 Rd imm8

ADD{<c>}{<q>} {<Rd>,} <Rn>, #<imm12> // (<imm12> cannot be represented in T1, T2, or T3)

ADDW{<c>}{<q>} {<Rd>,} <Rn>, #<imm12> // (<imm12> can be represented in T1, T2, or T3)

if Rn == '1111' then SEE "ADR";

if Rn == '1101' then SEE "ADD (SP plus immediate)";

d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);

if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c> See Standard assembler syntax fields.

<q> See Standard assembler syntax fields.

<Rdn> Is the general-purpose source and destination register, encoded in the "Rdn" field.

<imm8> Is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field.

<Rd> For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as

<Rn>. If the PC is used:

ADD, ADDS (immediate) Page 19

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