IEEE 802.3bj标准：100Gb/s在背板和铜缆上的物理层规范

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"IEEE 802.3bj-2014标准，是IEEE针对100Gbps速率在背板和铜缆上操作的物理层规范和管理参数的修正案，由IEEE LAN/MAN标准委员会赞助。此标准是对IEEE 802.3-2012标准的补充，同时考虑了IEEE 802.3bk-2013的修订内容。" "IEEE 802.3bj"标准详细说明了100 Gigabit Ethernet (100GBase) 在数据中心和高性能计算环境中的实现，特别是在背板和铜缆上的传输。这个标准是为了解决高速数据通信的需求，尤其是在高密度、短距离通信场景下，如服务器集群和交换机内部连接。它定义了物理层（PHY）的规格，包括编码、信号传输、接口和电气特性，以及管理和诊断参数。 1. **物理层规格**：在100GBase中，物理层被设计来支持100 Gbps的数据速率，这需要高级的信号处理技术，如PAM-4（四电平脉冲幅度调制）编码，以在有限的带宽内传输更多数据。标准还规定了信号的电气特性，包括阻抗匹配、信号完整性、噪声容限等，确保数据在铜缆和背板上的可靠传输。 2. **管理参数**：标准提供了网络管理和故障诊断的参数，如性能监控、错误检测和校正机制。这些参数帮助维护网络的稳定性和高效运行，通过实时监测和报告链路状态，及时发现并解决问题。 3. **背板和铜缆的挑战**：在背板上实现100Gbps通信面临散热、信号干扰和布线复杂性等问题。IEEE 802.3bj提供了解决方案，包括优化的布线布局、信号补偿算法和热管理策略，以克服这些挑战。 4. **兼容性和互操作性**：作为IEEE 802.3系列标准的一部分，802.3bj与其他802.3标准保持兼容，确保设备间的无缝连接和互操作性。这允许网络基础设施的逐步升级，而不会造成重大中断。 5. **技术发展和应用**：随着数据中心和云计算的快速发展，100Gbps的高速连接已经成为基础设施的关键组成部分。IEEE 802.3bj标准推动了硬件制造商开发出更高效、更紧凑的100Gbps网络设备，促进了高速网络技术的普及和进步。 "IEEE 802.3bj-2014"标准对于理解100Gbps Ethernet在背板和铜缆上的实现至关重要，它是现代数据中心和企业网络技术的重要里程碑，推动了高速网络的发展，并为未来更高速度的标准奠定了基础。

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45.2.1.7.4 Transmit fault (1.8.11).................................................... 18

45.2.1.7.5 Receive fault (1.8.10) ..................................................... 18

45.2.1.8 PMD transmit disable register (Register 1.9) .................................... 18

45.2.1.12 40G/100G PMA/PMD extended ability register (Register 1.13) ...... 20

45.2.1.12.1a 100GBASE-CR4 ability (1.13.14).................................. 20

45.2.1.12.1b 100GBASE-KR4 ability (1.13.13) ................................. 20

45.2.1.12.1c 100GBASE-KP4 ability (1.13.12).................................. 20

45.2.1.13a EEE capability (Register 1.16) .......................................................... 20

45.2.1.13a.1 100GBASE-CR4 EEE deep sleep supported (1.16.11).. 21

45.2.1.13a.2 100GBASE-KR4 EEE deep sleep supported (1.16.10).. 21

45.2.1.13a.3 100GBASE-KP4 EEE deep sleep supported (1.16.9) .... 21

45.2.1.13a.4 100GBASE-CR10 EEE deep sleep supported (1.16.8).. 21

45.2.1.13a.5 40GBASE-CR4 EEE deep sleep supported (1.16.1)...... 21

45.2.1.13a.6 40GBASE-KR4 EEE deep sleep supported (1.16.0)...... 21

45.2.1.79 BASE-R PMD control register (Register 1.150) ............................... 22

45.2.1.80 BASE-R PMD status register (Register 1.151) ................................. 22

45.2.1.81 BASE-R LP coefficient update, lane 0 register (Register 1.152) ...... 22

45.2.1.82 BASE-R LP status report, lane 0 register (Register 1.153) ............... 22

45.2.1.83 BASE-R LD coefficient update, lane 0 register (Register 1.154) ..... 22

45.2.1.84 BASE-R LD status report, lane 0 register (Register 1.155)............... 22

45.2.1.88a PMA overhead control 1, 2, and 3 registers

(Register 1.162 through 1.164) .......................................................... 23

45.2.1.88b PMA overhead status 1 and 2 registers (Register 1.165, 1.166)........ 23

45.2.1.92a RS-FEC control register (Register 1.200).......................................... 24

45.2.1.92a.1 FEC bypass indication enable (1.200.1)......................... 24

45.2.1.92a.2 FEC bypass correction enable (1.200.0)......................... 24

45.2.1.92b RS-FEC status register (Register 1.201)............................................ 25

45.2.1.92b.1 PCS align status (1.201.15) ............................................ 25

45.2.1.92b.2 RS-FEC align status (1.201.14)...................................... 25

45.2.1.92b.3 FEC AM lock 3 (1.201.11)............................................. 26

45.2.1.92b.4 FEC AM lock 2 (1.201.10)............................................. 26

45.2.1.92b.5 FEC AM lock 1 (1.201.9)............................................... 26

45.2.1.92b.6 FEC AM lock 0 (1.201.8)............................................... 26

45.2.1.92b.7 RS-FEC high SER (1.201.2)........................................... 26

45.2.1.92b.8 FEC bypass indication ability (1.201.1) ......................... 26

45.2.1.92b.9 FEC bypass correction ability (1.201.0)......................... 26

45.2.1.92c RS-FEC corrected codewords counter (Register 1.202, 1.203)......... 26

45.2.1.92d RS-FEC uncorrected codewords counter (Register 1.204, 1.205)..... 27

45.2.1.92e RS-FEC lane mapping register (Register 1.206) ............................... 27

45.2.1.92f RS-FEC symbol error counter lane 0 (Register 1.210, 1.211)........... 28

45.2.1.92g RS-FEC symbol error counter lane 1 through 3

(Register 1.212, 1.213, 1.214, 1.215, 1.216, 1.217) .......................... 28

45.2.1.92h RS-FEC BIP error counter lane 0 (Register 1.230) ........................... 28

45.2.1.92i RS-FEC BIP error counter, lane 1 through 19

(Registers 1.231 through 1.249) ........................................................ 28

45.2.1.92j RS-FEC PCS lane 0 mapping register (Register 1.250) .................... 29

45.2.1.92k RS-FEC PCS lanes 1 through 19 mapping registers

(Registers 1.251 through 1.269) ........................................................ 29

45.2.1.92l RS-FEC PCS alignment status 1 register (Register 1.280)................ 29

45.2.1.92l.1 Block 7 lock (1.280.7) .................................................... 30

45.2.1.92l.2 Block 6 lock (1.280.6) .................................................... 30

45.2.1.92l.3 Block 5 lock (1.280.5) .................................................... 30

45.2.1.92l.4 Block 4 lock (1.280.4) .................................................... 30

45.2.1.92l.5 Block 3 lock (1.280.3) .................................................... 30

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45.2.1.92l.6 Block 2 lock (1.280.2) .................................................... 31

45.2.1.92l.7 Block 1 lock (1.280.1) .................................................... 31

45.2.1.92l.8 Block 0 lock (1.280.0) .................................................... 31

45.2.1.92m RS-FEC PCS alignment status 2 register (Register 1.281)................ 31

45.2.1.92m.1 Block 19 lock (1.281.11) ................................................ 32

45.2.1.92m.2 Block 18 lock (1.281.10) ................................................ 32

45.2.1.92m.3 Block 17 lock (1.281.9) .................................................. 32

45.2.1.92m.4 Block 16 lock (1.281.8) .................................................. 32

45.2.1.92m.5 Block 15 lock (1.281.7) .................................................. 32

45.2.1.92m.6 Block 14 lock (1.281.6) .................................................. 32

45.2.1.92m.7 Block 13 lock (1.281.5) .................................................. 33

45.2.1.92m.8 Block 12 lock (1.281.4) .................................................. 33

45.2.1.92m.9 Block 11 lock (1.281.3) .................................................. 33

45.2.1.92m.10Block 10 lock (1.281.2) .................................................. 33

45.2.1.92m.11Block 9 lock (1.281.1) .................................................... 33

45.2.1.92m.12Block 8 lock (1.281.0) .................................................... 33

45.2.1.92n RS-FEC PCS alignment status 3 register (Register 1.282)................ 33

45.2.1.92n.1 Lane 7 aligned (1.282.7)................................................. 33

45.2.1.92n.2 Lane 6 aligned (1.282.6)................................................. 34

45.2.1.92n.3 Lane 5 aligned (1.282.5)................................................. 34

45.2.1.92n.4 Lane 4 aligned (1.282.4)................................................. 34

45.2.1.92n.5 Lane 3 aligned (1.282.3)................................................. 34

45.2.1.92n.6 Lane 2 aligned (1.282.2)................................................. 35

45.2.1.92n.7 Lane 1 aligned (1.282.1)................................................. 35

45.2.1.92n.8 Lane 0 aligned (1.282.0)................................................. 35

45.2.1.92o RS-FEC PCS alignment status 4 register (Register 1.283)................ 35

45.2.1.92o.1 Lane 19 aligned (1.283.11)............................................. 36

45.2.1.92o.2 Lane 18 aligned (1.283.10)............................................. 36

45.2.1.92o.3 Lane 17 aligned (1.283.9)............................................... 36

45.2.1.92o.4 Lane 16 aligned (1.283.8)............................................... 36

45.2.1.92o.5 Lane 15 aligned (1.283.7)............................................... 36

45.2.1.92o.6 Lane 14 aligned (1.283.6)............................................... 37

45.2.1.92o.7 Lane 13 aligned (1.283.5)............................................... 37

45.2.1.92o.8 Lane 12 aligned (1.283.4)............................................... 37

45.2.1.92o.9 Lane 11 aligned (1.283.3)............................................... 37

45.2.1.92o.10 Lane 10 aligned (1.283.2)............................................... 37

45.2.1.92o.11 Lane 9 aligned (1.283.1)................................................. 37

45.2.1.92o.12 Lane 8 aligned (1.283.0)................................................. 37

45.2.1.98a PMD training pattern lanes 0 through 3

(Register 1.1450 through 1.1453) ...................................................... 37

45.2.1.100 PRBS pattern testing control (Register 1.1501)................................. 38

45.2.3 PCS registers.......................................................................................................... 39

45.2.3.9 EEE control and capability (Register 3.20) ....................................... 39

45.2.3.9.a 100GBASE-R EEE deep sleep supported (3.20.13).......................... 40

45.2.3.9.b 100GBASE-R EEE fast wake supported (3.20.12) ........................... 40

45.2.3.9.c 40GBASE-R EEE deep sleep supported (3.20.9).............................. 40

45.2.3.9.d 40GBASE-R EEE fast wake supported (3.20.8) ............................... 40

45.2.3.9.7 LPI_FW (3.20.0)............................................................. 40

45.2.7 Auto-Negotiation registers..................................................................................... 40

45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48)............. 40

45.2.7.12.2 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3,

7.48.5, 7.48.6, 7.48.8, 7.48.9, 7.48.10, 7.48.11)............. 41

45.2.7.13 EEE advertisement (Register 7.60).................................................... 41

45.2.7.13.a 100GBASE-CR4 EEE supported (7.60.13).................... 43

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xvi

45.2.7.13.b 100GBASE-KR4 EEE supported (7.60.12)....................................... 43

45.2.7.13.c 100GBASE-KP4 EEE supported (7.60.11) ....................................... 43

45.2.7.13.d 100GBASE-CR10 EEE supported (7.60.10)..................................... 43

45.2.7.13.e 40GBASE-CR4 EEE supported (7.60.8)........................................... 43

45.2.7.13.f 40GBASE-KR4 EEE supported (7.60.7)........................................... 43

45.2.7.14 EEE link partner ability (Register 7.61) ............................................ 43

45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45,

Management Data Input/Output (MDIO) Interface............................................................... 45

45.5.3.2 PMA/PMD MMD options ................................................................. 45

45.5.3.3 PMA/PMD management functions.................................................... 45

69. Introduction to Ethernet operation over electrical backplanes .......................................................... 46

69.1 Overview................................................................................................................................ 46

69.1.1 Scope...................................................................................................................... 46

69.1.2 Objectives .............................................................................................................. 46

69.1.2 Relationship of Backplane Ethernet to the ISO OSI reference model................... 46

69.2 Summary of Backplane Ethernet Sublayers .......................................................................... 48

69.2.1 Reconciliation sublayer and media independent interfaces................................... 48

69.2.3 Physical Layer signaling systems .......................................................................... 49

69.2.6 Low-Power Idle ..................................................................................................... 50

69.3 Delay constraints.................................................................................................................... 50

69.5 Protocol implementation conformance statement (PICS) proforma...................................... 50

73. Auto-Negotiation for backplane and copper cable assembly ............................................................ 51

73.3 Functional specifications ....................................................................................................... 51

73.5 DME transmission ................................................................................................................. 51

73.5.1 DME electrical specifications................................................................................ 51

73.6 Link codeword encoding ....................................................................................................... 51

73.6.4 Technology Ability Field....................................................................................... 51

73.6.10 Transmit Switch function....................................................................................... 52

73.7 Receive function requirements .............................................................................................. 52

73.7.1 DME page reception .............................................................................................. 52

73.7.2 Receive Switch function ........................................................................................ 52

73.7.6 Priority Resolution function................................................................................... 53

73.10 State diagrams and variable definitions ................................................................................. 53

73.10.1 State diagram variables.......................................................................................... 53

73.11 Protocol implementation conformance statement (PICS) proforma for Clause 73,

Auto-Negotiation for backplane and copper cable assembly ................................................ 55

73.11.4 PICS proforma tables for Auto-Negotiation for backplane and

copper cable assembly ........................................................................................... 55

73.11.4.3 Link codeword encoding ................................................................... 55

73.11.4.4 Receive function requirements .......................................................... 56

74. Forward Error Correction (FEC) sublayer for BASE-R PHYs ......................................................... 57

74.5 FEC service interface............................................................................................................. 57

74.5.2 40GBASE-R and 100GBASE-R service primitives .............................................. 57

74.7 FEC principle of operation .................................................................................................... 57

74.7.4 Functions within FEC sublayer.............................................................................. 57

74.7.4.8 FEC rapid block synchronization for EEE (optional)........................ 58

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xvii

78. Energy-Efficient Ethernet (EEE) ....................................................................................................... 59

78.1 Overview................................................................................................................................ 59

78.1.1 LPI Signaling ......................................................................................................... 59

78.1.1.1 Interlayer Reconciliation sublayer service interfaces ........................ 60

78.1.2 LPI Client service interface ................................................................................... 60

78.1.2.2 LP_IDLE.indication........................................................................... 60

78.1.2.2.3 When generated .............................................................. 60

78.1.3 Reconciliation sublayer operation ......................................................................... 60

78.1.3.3 PHY LPI operation ............................................................................ 60

78.1.3.3.1 PHY LPI transmit operation ........................................... 60

78.1.3.3.2 PHY LPI receive operation............................................. 61

78.1.4 PHY types optionally supporting EEE Supported PHY types .............................. 61

78.2 LPI mode timing parameters description............................................................................... 62

78.3 Capabilities Negotiation ........................................................................................................ 62

78.4 Data Link Layer Capabilities................................................................................................. 63

78.4.2 Control state diagrams ........................................................................................... 63

78.4.2.3 Variables ............................................................................................ 63

78.4.2.4 Functions............................................................................................ 65

78.4.2.5 State diagrams.................................................................................... 66

78.4.3 State change procedure across a link ..................................................................... 67

78.4.3.1 Transmitting link partner’s state change procedure across a link...... 68

78.4.3.2 Receiving link partner’s state change procedure across a link .......... 68

78.5 Communication link access latency....................................................................................... 69

78.5.2 40 Gb/s and 100 Gb/s PHY extension using XLAUI or CAUI............................. 70

79. IEEE 802.3 Organizationally Specific Link Layer Discovery Protocol (LLDP) type,

length, and value (TLV) information elements ................................................................................. 71

79.3 IEEE 802.3 Organizationally Specific TLVs ........................................................................ 71

79.3.6 EEE Fast Wake TLV ............................................................................................. 71

79.3.6.1 Transmit fast wake............................................................................. 71

79.3.6.2 Receive fast wake .............................................................................. 72

79.3.6.3 Echo of Transmit fast wake and Receive fast wake .......................... 72

79.3.6.4 EEE Fast Wake TLV usage rules ...................................................... 72

79.4 IEEE 802.3 Organizationally Specific TLV selection management ..................................... 72

79.4.2 IEEE 802.3 Organizationally Specific TLV/LLDP Local and

Remote System group managed object class cross references .............................. 72

79.5 Protocol implementation conformance statement (PICS) proforma for

IEEE 802.3 Organizationally Specific Link Layer Discovery Protocol (LLDP)

type, length, and values (TLV) information elements ........................................................... 73

79.5.3 Major capabilities/options...................................................................................... 73

79.5.6a EEE Fast Wake TLV ............................................................................................. 74

80. Introduction to 40 Gb/s and 100 Gb/s networks ................................................................................75

80.1 Overview................................................................................................................................ 75

80.1.1 Scope...................................................................................................................... 75

80.1.2 Objectives .............................................................................................................. 75

80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the

ISO OSI reference model....................................................................................... 75

80.1.4 Nomenclature......................................................................................................... 76

80.1.5 Physical Layer signaling systems .......................................................................... 77

80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers ................................................ 79

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xviii

80.2.2 Physical Coding Sublayer (PCS) ........................................................................... 79

80.2.3 Forward Error Correction (FEC) sublayers ........................................................... 79

80.2.4 Physical Medium Attachment (PMA) sublayer..................................................... 79

80.2.5 Physical Medium Dependent (PMD) sublayer ...................................................... 79

80.2.6 Auto-Negotiation ................................................................................................... 79

80.3 Service interface specification method and notation ............................................................. 80

80.3.1 Inter-sublayer service interface.............................................................................. 80

80.3.2 Instances of the Inter-sublayer service interface.................................................... 80

80.3.3 Semantics of inter-sublayer service interface primitives....................................... 83

80.3.3.4 IS_TX_MODE.request ...................................................................... 83

80.3.3.4.1 Semantics of the service primitive.................................. 83

80.3.3.4.2 When generated .............................................................. 83

80.3.3.4.3 Effect of receipt .............................................................. 83

80.3.3.5 IS_RX_MODE.request...................................................................... 83

80.3.3.5.1 Semantics of the service primitive.................................. 83

80.3.3.5.2 When generated .............................................................. 83

80.3.3.5.3 Effect of receipt .............................................................. 83

80.3.3.6 IS_RX_LPI_ACTIVE.request ........................................................... 83

80.3.3.6.1 Semantics of the service primitive.................................. 84

80.3.3.6.2 When generated .............................................................. 84

80.3.3.6.3 Effect of receipt .............................................................. 84

80.3.3.7 IS_ENERGY_DETECT.indication ................................................... 84

80.3.3.7.1 Semantics of the service primitive.................................. 84

80.3.3.7.2 When generated .............................................................. 84

80.3.3.7.3 Effect of receipt .............................................................. 84

80.3.3.8 IS_RX_TX_MODE.indication .......................................................... 84

80.3.3.8.1 Semantics of the service primitive.................................. 84

80.3.3.8.2 When generated .............................................................. 85

80.3.3.8.3 Effect of receipt .............................................................. 85

80.4 Delay constraints.................................................................................................................... 85

80.5 Skew constraints .................................................................................................................... 85

80.7 Protocol implementation conformance statement (PICS) proforma...................................... 89

81. Reconciliation Sublayer (RS) and Media Independent Interface for 40 Gb/s and

100 Gb/s operation (XLGMII and CGMII) ....................................................................................... 90

81.1 Overview................................................................................................................................ 90

81.1.1 Summary of major concepts .................................................................................. 90

81.1.7 Mapping of XLGMII/CGMII signals to PLS service primitives........................... 90

81.1.7.3 Mapping of PLS_CARRIER.indication ............................................ 90

81.3 XLGMII/CGMII functional specifications............................................................................ 91

81.3.1 Transmit ................................................................................................................. 91

81.3.1.2 TXC<7:0> (transmit control)............................................................. 91

81.3.1.5 Transmit direction LPI transition....................................................... 91

81.3.2 Receive...................................................................................................................92

81.3.2.2 RXC<7:0> (receive control) .............................................................. 92

81.3.2.4 Receive direction LPI transition ........................................................ 92

81.3.4 Link fault signaling................................................................................................ 92

81.3a LPI Assertion and Detection.................................................................................................. 93

81.3a.1 LPI messages ......................................................................................................... 94

81.3a.2 Transmit LPI state diagram.................................................................................... 94

81.3a.2.1 Variables and counters....................................................................... 94

81.3a.2.2 State diagram ..................................................................................... 95

81.3a.3 Considerations for transmit system behavior......................................................... 95

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