Vivado设计套件：FPGA/自适应SoC I/O和时钟规划指南

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"Xilinx FPGA UG 899 - I/O和时钟规划是FPGA/自适应SoC设计中的重要环节，涉及到信号布局、信号完整性和电源管理等多个方面。该文档是Vivado Design Suite用户指南，针对2023.1版本，旨在帮助设计者优化设计流程，处理PCB与FPGA之间的交互，以及适应不断变化的行业标准。" 在FPGA开发过程中，I/O和时钟规划是至关重要的步骤，它决定了设计的性能和可靠性。这份用户指南详细阐述了以下几个关键知识点： 1. **I/O规划**：设计者需要考虑如何将不同类型的信号分配到FPGA的物理引脚上，以减少信号路径长度和交叉，从而提高信号完整性和降低电磁干扰。对于高速信号，必须特别注意确保其完整性，避免信号失真和反射。 2. **时钟规划**：时钟是数字系统的心跳，正确的时钟分配能保证系统定时正确，防止时序违规。设计者需要考虑时钟网络的延迟，以及时钟源的分布和同步，以满足设计的时序约束。 3. **电源和接地**：良好的电源和接地规划是保证信号完整性和降低噪声的关键。设计者需要评估PCB上的电源和接地信号的可用性，并根据需求规划去耦电容，确保稳定供电和低阻抗返回路径。 4. **兼容性**：在I/O规划中，需要考虑设备可能的配置，使其能与备用设备协同工作，增加设计的灵活性和可扩展性。 5. **PCB设计**：设计者需协调PCB设计者的需求，确保信号布线的简洁性和高效性，同时避免信号路径间的干扰。 6. **设备编程和调试**：规划阶段需要识别设备的编程和调试接口，确保这些功能在实际操作中能够顺利进行。 7. **非包容性语言更新**：AMD Adaptive Computing正在逐步移除产品和相关资料中的非包容性语言，以创造一个更包容的工作环境和用户体验。本指南按照设计流程组织内容，涵盖了从基础概念到具体技术实施的各个阶段，包括使用Platform Board Flow进行I/O和时钟规划的方法，对不同技术（如SSIT，Zynq UltraScale+ MPSoCs，UltraScale和UltraScale+，以及Versal Adaptive SoC）的特定I/O规划策略，以及配置设备的细节等。通过深入阅读和理解这份用户指南，FPGA和系统设计者可以更好地规划他们的设计，优化性能，减少潜在问题，并与最新的行业标准保持一致。

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I/O Planning for Zynq UltraScale+ MPSoCs

Because of the advanced capabilies of the AMD Zynq™ UltraScale+™ MPSoCs, the pin planning

ow diers from other devices. You must go through IP customizaon for the

Zynq UltraScale+ MPSoC IP to indicate the features you plan to use in your design. As you go

through the design ow, the mulplexed I/O (MIO) pins do not show up in the user design or

constraints. The I/O Planning Project does not show the ulizaon of the MIO ports, nor does it

write out the placement for the MIO pins. The only way to see a full list of the used pins for a

schemac or for communicang with the board designer, is by using the File → Export → Export

I/O Ports command to generate a CSV le. AMD recommends using an HDL project for all pin

planning in Zynq UltraScale+ MPSoCs. For more informaon, see Dening and Conguring I/O

Ports.

Related Information

Dening and Conguring I/O Ports

I/O Planning for UltraScale and UltraScale+

The bank types names are dierent in UltraScale and UltraScale+ devices from what they are in

7 series devices. Addional I/O standards have also been added. In 7 series devices, the bank

types were High Range and High Performance; in UltraScale architecture devices, the names are

High Density (replacing High Range), and High Performance. For more informaon, see secon

Introducon to High Density I/O Banks in the UltraScale Architecture SelectIO Resources User

Guide (UG571).

I/O Planning for Versal Adaptive SoC

The two primary types of I/O in Versal adapve SoCs are high-performance XP I/O (XPIO) and

high density HD I/O (HDIO). The XPIO includes dedicated logic to support high-speed interfaces

with voltage ranges between 1.0 V and 1.5 V. HDIO and XPIO banks do not have overlapping

voltages or I/O standards. The HDIO supports interfaces with voltages ranging from 1.8 V to 3.3

V. The HDIO provides logic for both single data rate (SDR) and double data rate (DDR) interfaces

at reduced clocking speeds. See Versal Adapve SoC SelectIO Resources Architecture Manual

(AM010) for architecture informaon and Vivado Design Suite Properes Reference Guide (UG912)

for detailed informaon on Advanced IO Wizard/Advanced IO Planner.

Chapter 1: Introduction

UG899 (v2023.1) May 16, 2023

Vivado Design Suite User Guide: I/O and Clock Planning 16

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Each conguraon mode has a corresponding set of interface pins that span one or more I/O

banks on the device. Bank 0 contains the dedicated conguraon pins and is always a part of

every conguraon interface. Bank 65 in AMD UltraScale™ and AMD UltraScale+™ devices and

Banks 14 and 15 in 7 series devices contain mulfuncon pins that are used in various

conguraon modes. For informaon on the available device conguraon modes, see the

Conguraon User Guide for your device. For informaon on analyzing how the conguraon

modes might conict with other mulfuncon pins, see Mulfuncon Pins.

To set device conguraon modes and view informaon about the modes:

1. Select Tools → Edit Device Properes.

2. In the Edit Device Properes dialog box (see the following gure), select the Conguraon

Modes category, do the following, and click OK to close the dialog box:

• Enable the check box for a conguraon mode to set that conguraon mode. When you

set a conguraon mode:

○ The associated I/O pins display in the Cong column of the Package Pins window.

○ The following constraints are created when you save the design:

set_property BITSTREAM.CONFIG.PERSIST NO [current_design]

set_property CONFIG_MODE <configuration_mode> [current_design]

• Click a conguraon mode to open a dialog box in which you can view informaon,

including a descripon, conguraon diagram, and links to more informaon. Click Print to

print the conguraon diagram.

• Enable Prohibit usage of the conguraon pins as user I/O and persist aer conguraon

to ensure that pins are used as conguraon pins and not as general purpose I/Os aer

conguraon. When you select this opon, the following constraint is created when you

save the design:

set_property BITSTREAM.CONFIG.PERSIST YES [current_design]

Note: For more informaon on the conguraon bitstream sengs, see secon Device

Conguraon Bitsream sengs in the Vivado Design Suite User Guide: Programming and Debugging

(UG908).

IMPORTANT! The JTAG conguraon mode is always selected. You can select one conguraon

mode in addion to the JTAG conguraon mode.

Chapter 2: Configuring the Device

UG899 (v2023.1) May 16, 2023

Vivado Design Suite User Guide: I/O and Clock Planning 20

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