STV0299B: 机顶盒QPSK/BPSK解调芯片技术规格

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"STV0299B是用于机顶盒的TUNNER驱动芯片，主要功能包括QPSK和BPSK调制解调，适用于多种标准，具备低误码率性能，宽载波环路跟踪范围，以及低功耗、集成式模拟-to-数字转换器等特性。该芯片还包含数字AGC、数字滤波器、定时恢复、Viterbi软解码器、Reed-Solomon外解码器等功能，支持高达90Mbps的信道比特率和1到50Msymbols/s的符号频率率。" STV0299B是一款由意法半导体（STMicroelectronics）开发的高级链接集成电路，专为机顶盒中的调谐器应用设计。这款芯片支持QPSK（正交相移键控）和BPSK（二进制相移键控）调制解调，使其能够处理多种广播标准，例如数字卫星电视(DVB-S)或地面电视(DVB-T)。由于其预设为初步信息，因此细节可能在产品最终发布时有所变化。该芯片的一大优点是易于实现且成本效益高，特别适合与低成本的直接转换调谐器配合使用。STV0299B能够在存在同频道干扰的情况下保持极低的误比特率（BER），确保信号传输的稳定性。此外，它具有宽范围的载波环路跟踪能力，能补偿因天线或馈线引起的频率漂移，保持信号锁定。 STV0299B集成了一对6位模拟-to-数字转换器，用于将接收的模拟信号转换为数字信号，以及双数字自动增益控制（AGC），以确保输入信号强度的一致性。数字Nyquist根滤波器提供了0.35或0.20的滚降系数，以减少带外干扰。数字载波环路带有锁检测器、宽范围的偏置旋转器和跟踪环路（典型值±45MHz），确保精确的载波同步。定时恢复功能内置了锁检测器，确保数据流的时间同步。芯片支持的信道比特率高达90Mbps，符号频率率可从1到50Msymbols/s进行调整，适应不同类型的广播服务。 STV0299B内部包含了内解码器和外解码器。内解码器采用Viterbi软解码器处理卷积码，支持M=7，速率1/2的编码，同时兼容1/2、2/3、3/4、5/6、6/7和7/8的穿孔码。同步提取功能有助于识别和分离数据流。外解码器则是一个Reed-Solomon解码器，能够处理16个奇偶校验字节，最多纠正8个字节错误，增强了纠错能力。总体而言，STV0299B驱动芯片以其高效能、低功耗和全面的信号处理能力，为机顶盒的数字电视接收提供了可靠的解决方案。

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STV0299B

7/36

4 FUNCTIONAL DESCRIPTION

The STV0299B is a multistandard demodulator

and error correction decoder IC for the reception

of QPSK and BPSK modulated signals. It is

intended for use in digital satellite television

applications. The IC can accept two standards of

QPSK modulated signals (DVB and DSS) as well

as BPSK modulated signals over a wide symbol

frequency range (from 1 to 50 Msymbols/s). The

signals are digitized via an integrated dual 6-bit

analog to digital converter, and interpolated and

digitally filtered by a Nyquist root filter (with a

settable roll-off value of either 0.35 or 0.20).

There are two built-in digital Automatic Gain

Controls (AGCs). The first AGC allows the tuner

gain to be controlled by the pulse density

modulated output. The second AGC performs

power optimization of the digital signal bandwidth

(internal to the STV0299B). The digital signal then

passes through the digital carrier loop fitted with

an on-chip derotator and tracking loop, lock

detector, and digital timing recovery.

Forward error correction is integrated by way of an

inner Viterbi soft decoder, and an outer

Reed-Solomon decoder.

4.1 Front End Interfaces

4.1.1 I

C Interface

The standard I

C protocol is used whereby the

first byte is Hex D0 for a write operation, or Hex

D1 for a read operation. The I

C interface

operates differently depending on whether it is in

normal or standby mode.

4.1.2 Write Operation (Normal Mode)

The byte sequence is as follows:

1 The first byte gives the device address plus the

direction bit (R/W = 0).

2 The second byte contains the internal address

of the first register to be accessed.

3 The next byte is written in the internal register.

Following bytes (if any) are written in

successive internal registers.

4 The transfer lasts until stop conditions are

encountered.

5 The STV0299B acknowledges every byte

transfer.

4.1.3 Read Operation (Normal Mode)

The address of the first register to read is

programmed in a write operation without data, and

terminated by the stop condition. Then, another

start is followed by the device address and R/

W = 1. All following bytes are now data to be read

at successive positions starting from the initial

address. Figure 2 shows the I

C Normal Mode

Write and Read Registers.

4.1.4 I

C Interface in Standby Mode

Only three registers can be addressed while in

standby mode: RCR (address 01 Hex), MCR

(address 02 Hex) and ACR (address 03 Hex).

These three registers can be either read or written

to (refer to Figure 3).

Only one register may be read or written to per

sequence (no increment). While in standby mode,

the Serial Clock (SCL) frequency must be lower than

one tenth of the CLK_IN frequency (f

CLK_IN

/ 10).

Figure 2:

C Read and Write Operations in Normal Mode

Figure 3:

C Read and Write Operations in Standby Mode

Write registers 0 to 3 with AA, BB, CC, DD

Read registers 2 and 3

Start

Device

Address,

Write D0

ACK

Address

ACK

Data

ACK

Data

ACK

Data

ACK

Data

ACK Stop

Start Device Address, Write D0 ACK Register Address 02 ACK Stop

Start

Device Address,

Read D1

ACK Data Read CC ACK Data Read DD

ACK

Stop

Write operation

Read operation

Start Device Address, Write D0 ACK Register Address 01, 02 or 03 ACK Data ACK Stop

Start

Device Address

, Read D0

ACK Register Address ACK Stop

Start

Device Address,

Read D1

ACK Reader Data

ACK (or no

ACK

)

Stop

Note: 1

ACK is not absolutely necessary after Data

STV0299B

8/36

4 FUNCTIONAL DESCRIPTION

(continued)

4.1.5 Specific Concerns about SCL

Frequency

For reliable operation in Normal Mode, the SCL

frequency must be lower than 1/40 of the Master

Clock (M_CLK) frequency. Consequently, care

should be taken to observe the following:

1 Before returning to Normal Mode from Standby

Mode, the M_CLK frequency must be selected

such that f

M_CLK

≥

40 f

SCL

2 After Power-on reset signal, the STV0299B

operates in Normal Mode. There are two possi-

ble cases:

- DIRCLK-DIS (pin 58) is grounded.

M_CLK = CLK_IN, the f

SCL

frequency of the

C bus must satisfy:

- DIRCLK-DIS (pin 58) is tied to V

(where ), and the f

SCL

frequency of the I

C bus must satisfy:

and

SCL

≤

400 kHz.

For example, this second operating mode is

required when the application features both a

4 MHz XTAL and a 400 kHz I

C bus.

4.1.6 Identification Register

The Identification Register (at address Hex 00)

gives the release number of the circuit.

The content of this register at reset is presently A1

(same as STV0299).

4.1.7 Sampling Frequency

The STV0299B converts the analog inputs into

digital 6-bit I and Q flows. The sampling frequency

is f

M_CLK

which is derived from an external

reference described in Section 4.1.8

‘Clock

Generation’

. The maximum value of f

M_CLK

is 90

MHz.

The sampling causes the repetition of the input

spectrum at each integer multiple of f

M_CLK

. One

has to ensure that no frequency component is

folded in the useful signal bandwidth of f

(1+

)/2

where f

is the symbol frequency, and

is the

roll-off value.

4.1.8 Clock Generation

An integrated VCO (optimised to run in the range

of 300 to 400 MHz) is locked to a reference

frequency provided by a crystal oscillator by the

following relation:

The VCO’s loop filter is optimized for a reference

frequency between 4 and 8 MHz.

The VCO generates the following by division:

• The Master Clock (M_CLK)

• An auxiliary clock (AUX_CLK) which may either

be in the MHz range or in the 25 Hz to 1500 Hz

range for some specific LNB control (for

example, 60 Hz).

• A lower frequency, F22, typically 22 KHz,

needed for LNB control or DiSEqC

control.

When DIRCLK_CTRL = 1, the crystal signal is

routed directly to M_CLK; the VCO may still be

used to generate AUX_CK and/or the F22 (used

by the DiSEqC

interface).

If the internal VCO is not used by any of the

dividers, it may be stopped in order to decrease

the power consumption and/or radiation

emissions. The only guaranteed function in

standby mode is the I

C Write/Read function of

the three clock control registers.

There are restrictions on the high and low level

durations, and on the crystal (or external clock)

frequency when the direct clock is used.

These restrictions are explained in Section 4.1.5

Specific Concerns about SCL Frequency

SCL

CLK_IN

------------------- --

≤

M_CLK

100

----------

CLK_I

⋅

SCL

100

16 40

-------------------

CLK_IN

⋅≤

VCO

ref

4M1

()⋅⋅

XTAL

--------------

⋅⋅

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