MT41K128M16JT: 1.35V DDR3L SDRAM低电压版本特性与规格

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MT41K128M16JT是一款低电压（1.35V）的DDR3L SDRAM内存模块，它是1.5V DDR3 SDRAM的低功耗版本。这款内存设备在设计上兼容1.5V工作模式，并具备以下关键特性： 1. **电压规格**：该内存支持1.35V (1.283V 至 1.45V) 的VDD和VDDQ电压，对于需要更低功耗的系统非常合适，同时也向下兼容1.5V±0.075V的工作范围。 2. **接口与信号**：它采用差分双向数据 strobe（允许双向数据传输），以及两个差分时钟输入（CK 和 CK#），确保了高效和稳定的通信。 3. **架构细节**：拥有8个内部银行，每个银行具有8位预取（8n-bit prefetch）架构，这有助于提高数据处理速度。 4. **控制选项**：内存提供可编程的CAS (读取) 、POSTED CAS (附加读取) 和写入延迟（CL、AL、CWL），以及固定长度的突发模式（BL）和突发切片（BC）控制，可通过模数寄存器集（MRS）进行动态调整。 5. **刷新功能**：支持自刷新模式，以降低功耗。温度范围内刷新周期不同，如在0°C到+85°C之间可以实现每64毫秒8192次刷新，在+85°C到+95°C下则为每32毫秒一次。 6. **自我管理和优化**：内存还包含自动自刷新（ASR）功能，以适应不同工作条件下的自动管理，以及写电平校准，确保数据准确无误。 7. **多用途功能**：配备一个多功能寄存器，能够满足多种系统配置需求。 8. **包装与标记**：提供的选项包括512M x 4配置，明确标识为512M4，以及256M x 8配置。总结来说，MT41K128M16JT是一款高性能且低功耗的DDR3L SDRAM，适用于对电源效率有高要求的应用场景，提供了丰富的控制选项和适应性强的刷新策略，是现代计算机系统中存储解决方案的理想选择。

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 Ball Assignments (Top View)

1234 67895

DDQ

SSQ

REFDQ

ODT

SSQ

DQ2

NF, DQ6

DDQ

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

NF, DQ7

CK#

A10/AP

A12/BC#

A11

A14

DDQ

SSQ

DDQ

CKE

SSQ

DQ3

NF, DQ5

REFCA

BA1

Notes:

1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef83ed2952

2Gb_DDR3L.pdf - Rev. L 10/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[14:13],

A12/BC#, A11,

A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-

cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-

ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-

vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active

power-down (row active in any bank). CKE is synchronous for power-down entry and exit

and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-

ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-

cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-

nal rank selection on systems with multiple ranks. CS# is considered part of the command

code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with the input data during a write access. Although the DM

ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM

is referenced to V

REFDQ

. DM has an optional use as TDQS on the x8 device.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the

x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the

LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

DDQ

and DC LOW ≤

0.2 × V

DDQ

. RESET# assertion and deassertion are asynchronous.

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-

enced to V

REFDQ

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef83ed2952

2Gb_DDR3L.pdf - Rev. L 10/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A13, A12/BC#,

A11, A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (LDQS, LDQS#, UDQS, UDQS#) is referenced to the crossings of CK and

CK#.