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Spartan-7 FPGAs
Notes:
1. Packages with the same last letter and number sequence, e.g., A484, are footprint compatible with all other Spartan-7 devices with the same sequence. The footprint compatible devices within this family are outlined.
I/O Optimization at the Lowest Cost and
Highest Performance-per-Watt
XC7S6 XC7S15 XC7S25 XC7S50 XC7S75 XC7S100
6,000 12,800 23,360 52,160 76,800 102,400
938 2,000 3,650 8,150 12,000 16,000
CLB Flip-
7,500 16,000 29,200 65,200 96,000 128,000
Block RAM/FIFO w/ ECC (36 Kb each)
180 360 1,620 2,700 3,240 4,320
Clock Mgmt Tiles (1 MMCM + 1 PLL)
Max. Differential I/O Pairs
Embedded Hard IP
Resources
Analog Mixed Signal (AMS) / XADC
Configuration AES / HMAC Blocks
-1,-2 -1,-2 -1,-2 -1,-2 -1,-2 -1,-2
Industrial Temp
-1,-2,-1L -1,-2,-1L -1,-2,-1L -1,-2,-1L -1,-2,-1L -1,-2,-1L
-1 -1 -1 -1 -1 -1
Package
(1)
Body
(mm)
Ball Pitch
(mm) Available User I/O: 3.3V SelectIO™ HR I/O
CPGA196 8x8 0.5 100 100
CSGA225 13x13 0.8 100 100 150
CSGA324 15x15 0.8 150 210
FTGB196 15x15 1.0 100 100 100 100
FGGA484 23x23 1.0 250 338 338
FGGA676 27x27 1.0 400 400