TimeQuest时序分析详指南：Altera设计者必读

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"TimeQuest时序分析是一份详尽的Altera工具TimeQuest使用指南，由Ryan Scoville编撰于2010年9月30日。这份文档的诞生源于作者Ryan在过去的几年里对设计者们提供帮助时积累的大量经验，他发现需要不断重复解释相似的概念，特别是在Altera论坛上。为了系统化他的知识，他将自己关于TimeQuest的理解整理成了一本参考手册，尽管它仍在发展中，部分章节尚待完善。文档的核心内容已经相当全面，涵盖了TimeQuest的基础至高级功能，足以满足大多数用户的需求。然而，鉴于篇幅较长，作者建议读者利用文档中的书签功能，以便快速定位主要观点和关键信息。由于文档中的很多概念相互关联，通过书签和目录可以更有效地导航，减少理解过程中的困惑。比如，作者提到，每个示例常常需要其他部分的背景来解释，通过超链接和书签的结合，可以更好地引导用户浏览。首先推荐阅读的是"Getting Started"部分，这部分旨在提供一个全面的入门指导，让读者快速熟悉TimeQuest的基本操作流程和设计理念。随着深入学习，用户可以根据自己的需求和进度选择性地探索后续章节，如时序分析方法、性能优化策略、问题诊断与解决等。虽然文档可能存在一些空白或未涵盖的部分，但现有的内容已经足够为那些想要深入了解和掌握TimeQuest的工程师提供宝贵的参考资源。 TimeQuest时序分析文档是一个实用的学习工具，不仅包含了丰富的实战经验和理论知识，而且注重用户体验，提供了有效的导航手段。对于希望通过实践提高时序分析技能的设计师，这份文档无疑是一份不可或缺的参考资料。"

As can be seen, we just described a circuit outside the FPGA. We also now have a

FPGA.

Step 3) Determine the default setup and hold relationship between the

FPGA clock and virtual clock

This step requires the user to determine the setup and hold relationship between the clock

inside the FPGA and the virtual external clock. This is usually very straightforward, as in most

cases the launch clock and latch clock have the same period and are edge aligned, and hence

have a setup relationship equal to the clock period, and a hold relationship of 0ns, as shown in

the top-left example:

For I/O, the virtual clock will be the launch clock for input constraints, and the latch

clock for output constraints. I've shown a few more cases, but won't delve into too much detail

on how to determine the setup and hold relationship, which is covered in-depth in Timing

Analysis Basics.

Rather than delve into calculating the relationship, I'll show how TimeQuest will show

the relationship it is using, and hence the user doesn't have to figure it out beforehand. For

example, a user might have a 100MHz clock coming into the FPGA, which goes through a PLL

that outputs a 100MHz clock. After following the previous steps, the user creates a 10ns external

clock and applies it to the output ports like so:

create_clock -period 10.0 -name tx_clk_ext

set_output_delay -clock tx_clk_ext -max 0.0 [get_ports {TX_DATA[*] TX_PAR}]

set_output_delay -clock tx_clk_ext -min 0.0 [get_ports TX_DATA[*] TX_PAR}]

In this example, they've created a virtual clock called tx_clk_ext. They also said the ports

TX_DATA[*] and TX_PAR drive external registers clocked by tx_clk_ext, and the max and min

delay to those registers is 0.0ns. Since the internal clock also has a period of 10.0ns, and neither

is phase-shifted, then the default setup relationship is 10.0ns and the default hold relationship is

0.0ns. If the user is unsure of this, they can read in the .sdc file using the iterative method and

run report_timing to those ports. In TimeQuest's pull-down menu: Reports -> Custom Reports -

> Report Timing. Simply put the virtual clock name, tx_clk_ext, in the To Clock section, and run

report_timing twice, once for setup and once for hold. In this example, I got the following two

reports:

The left panel is the setup analysis, and the Relationship column, shown in red, is 10ns.

This is expected, as we have a 10ns clock feeding another 10ns clock. Below the Summary of

Paths is the detail for the first path. The 10ns is used such that the launch edge time is 0ns and

the latch edge time is 10ns. Likewise for hold analysis, the relationship is 0ns. The launch edge

time is 0ns and the latch edge time is 0ns.

So what is this really saying? When the launch clock comes into the FPGA, travels to the

source register, which is the output register in this case, then through the output port to the

external register, it must get there in greater than 0ns(the hold relationship) and less than

10ns(the setup relationship). Since our external -max and -min delays are 0ns, i.e. there is no

external delay, than the delay within the FPGA must be greater than 0ns and less than 10ns. At

this point, we have a full constraint that TimeQuest can analyze, but it is probably not the

analysis we want.

Step 4) Add multicycles

This step is usually unnecessary. But if step 3) resulted in a default analysis that is

incorrect, the user may want to modify the setup and hold relationships with multicycles. The

most common cases for this are when the user wants to open the window or shift the window.

Note that we are not accounting for external delays like the Tsu or Tco of an external device or

board delays, as that will be done in step 5. This step is just to make sure the clock relationships

are correct.

An example would be interfacing to a flash device that takes multiple clock cycles to

perform each operation, than the user may want to open the window

. An example may look like

so:

set_multicycle_path -setup -to [get_ports {FLASH_DATA[*]}] 4

set_multicycle_path -hold -to [get_ports {FLASH_DATA[*]}] 3

These two assignments tell TimeQuest that there are 4 clock cycles for the

FLASH_DATA to get out of the FPGA. So if the original setup and hold relationships were

10ns and 0ns, they would now be 40ns and 0ns(assuming the clock period is 10ns).

If the clock inside the FPGA has a phase-shift, generally through a PLL, and the external

clock does not, then the user may want to shift the window. For example, if the FPGA clock

feeding an output register were phase-shifted -500ps in order to help meet output timing, the

default setup relationship would be 500ps. To shift the window, the user would add:

set_multicycle_path -setup -to [get_ports {FLASH_DATA[*]}] 2

or:

set_multicycle_path -setup -from [get_clocks {pll|clk[0]} -to [get_clocks clk_ext] 2

The first one modifies the clock relationship on the output path, while the second one

modifies all relationships between these clocks. Either one of these will work as long as they

cover what the user wants covered. If the clocks have a 10ns period, the multicycle will modify

the setup relationship from 0.5ns to 9.5ns, and the hold relationship from -9.5ns to 0.5ns.

Note that if the FPGA clock were phase-shifted forward a little, then a multicycle would

most likely not be necessary. If the default setup relationship were 10ns, and the source clock

inside the FPGA were phase-shifted 500ps forward, then the default relationship would become

9.5ns, which is probably what the user wants.

Inputs work the opposite, whereby if the user phase-shifts the latching clock inside the

FPGA forward a little, then they probably want a multicycle to shift the window, but if they

phase-shift the clock back, they probably do not. This is easily seen by drawing the launch and

latch clock waveforms, as explained in the section on default setup and hold, specifically the

affect of phase-shifts.

Step 5) Modify the -max and -min delays to account for external delays.

Now that we have the correct setup and hold relationship, it is time to modify the -max

and -min values. They are currently set to 0, which means there is no external delay to the

data window is used by the external device and board delays, only leaving part of the data

window for the FPGA. The -max and -min values account for these external delays. Let's see

how they affect the analysis before determining how they account for external delays.

With both -max and -min at 0, we are stating that there are no external delays, and

basically have no affect on the analysis. As the -max value gets larger, it cuts into our setup

relationship. So if the our default setup relationship were 10ns, and the -max output delay were

4ns, that would mean the FPGA must get it's data out in less than 6ns to meet timing. Note the

setup relationship is still 10ns, but the FPGA's delay plus the external delay must be less than

that. So the larger -max gets, the more quickly the FPGA needs to get its data out and the harder

it is to meet timing. As the -max value gets larger, the FPGA needs a faster Tco.

The -min value is often more confusing because it works in the opposite way, whereby

the smaller it gets, the harder it is to meet timing. If the hold relationship is 0ns, and the -min

value was -1ns, then the only way to meet timing would be for the FPGA to get its data out in

more than 1ns. Looking at this through waveforms:

The top waveform shows the default relationships, while the second waveform shows

what happens after accounting for the external delays. Rather than the FPGA needing to get it's

data out between 0ns and 10ns, it must now get out between 1ns and 6ns. Likewise, for internal

paths, if a user entered similar external delays:

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